I think I found the issue. The Apollo3 sheet indicates that the ADC uses a 4pF sampling cap
https://ambiq.com/wp-content/uploads/20 … asheet.pdf
19.3.2 ADC Sample-and-Hold Time
The ADC on the Apollo3 Blue is a successive approximation register (SAR) ADC with 4 pF input capacitance. If there is large input impedance to the ADC input, then the sample-and-hold time must be increased to ensure the 4 pF sampling capacitor has time to settle.
The Apollo3 Blue ADC sample-and-hold time is fixed at 5 ADC clock cycles. The ADC has two options for ADC sampling clock, HFRC or HFRC/2. This results in a sample-and-hold time of approximately 0.2 µs for 24 MHz HFRC/2 ADC clock or about 0.1 µs for the default 48 MHz HFRC ADC clock.
The time constant calculation is given here: https://ambiq.com/wp-content/uploads/20 … elines.pdf
A rough estimation of time constant is:
TC (nsec) = input impedance (kohm) x input capacitance (pF)
Assuming no external capacitance on the ADC input, a conservative value of 6 pF (the 4 pF ADC capacitance plus a couple pF for package pin impedance) can be used.
TC = 200k * 6 = 1.2uSec
The required hold time to guarantee that the capacitance has settled (charged/discharged) to meet target accuracy is:
5% accuracy (3TC): 3 * 1.2 µs = 3.6 µs
1% accuracy (5TC): 5 * 1.2 µs = 6 µs
10-bit accuracy (7TC): 7 * 1.2 µs = 8.4 µs
Therefore the sample and hold time is about 20 times too short even for 5% accuracy.
The solution is fairly simple for slow moving inputs like mine. Just add a cap between the ADC input and ground. I used a 1uF cap and the results now agree with my measured voltage.