# Halt problem **URL:** \ **Category:** MicroMod\ **Tags:** arm-lpc\ **Created:** [July 25, 2006, 1:11pm UTC](https://community.sparkfun.com/t/halt-problem/2288 "2006-07-25T13:11:46Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![tecnologia](https://avatars.discourse-cdn.com/v4/letter/t/bcef8e/32.png) [@tecnologia](https://community.sparkfun.com/u/tecnologia)\ **Post date:** [July 25, 2006, 1:11pm UTC](https://community.sparkfun.com/t/halt-problem/2288/1 "2006-07-25T13:11:46Z")
We are starting to test a development environment using the components listed below. The problem that we are facing is that we **can’t get the OpenOCD to halt the target**. At times that we can we are enabled to inspect the registers, alter the registers, load a binary and execute it. When we try to step the program it works for about 3 steps after that it looses control over the target. For me it seems like a problem related to the JTAG resets, thou I have already tried some combinations parameters of the reset\_config [combination] [trst\_type] [srst\_type]. I have listed the configuration file, the command line used and the log of the openOCD. At this time we have exausted our knowledge and if someone can help we would appreciate. **environment** : SuSE Linux 10, kernel 2.6.13-15-default Open On-Chip Debugger (2006-07-15 12:00 CEST) Amontec JTagkey libftd2xx0.4.10.tar.gz Cirrus EDB9302 kit, uses EP9302 (ARM920T) microcontroller OpenOCD **arm9\_ftd2xx.cfg** : #daemon configuration telnet\_port 4444 gdb\_port 3333 #interface interface ftd2xx ftd2xx\_device\_desc “Amontec JTAGkey A” ftd2xx\_layout “jtagkey” ftd2xx\_vid\_pid 0x0403 0xcff8 jtag\_speed 1 #use combined on interfaces or targets that can’t set TRST/SRST separately reset\_config trst\_and\_srst #jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) jtag\_device 4 0x1 0xf 0xe #target configuration daemon\_startup halt #target target arm920t little run\_and\_halt run\_and\_halt\_time 0 30 **Starting the OpenOCD Server** openocd -f doc/configs/arm9\_ftd2xx.cfg -d 3 -l openocd.log **OpenOCD telnet command line** > Open On-Chip Debugger > reset > halt requesting target halt… > poll target state: running > reset halt > reset halt **openocd.log** Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: target.c:1275 handle\_reset\_command(): Debug: arm7\_9\_common.c:649 arm7\_9\_assert\_reset(): target-\>state: running Debug: jtag.c:234 jtag\_call\_event\_callbacks(): jtag event: 0 Debug: jtag.c:1044 jtag\_reset\_callback(): Debug: ftd2xx.c:614 jtagkey\_reset(): trst: 0, srst: 1, high\_output: 0x01, high\_direction: 0x0f Debug: arm7\_9\_common.c:775 arm7\_9\_halt(): target-\>state: reset Debug: embeddedice.c:251 embeddedice\_write\_reg(): 9: 0xffffffff Debug: embeddedice.c:251 embeddedice\_write\_reg(): 11: 0xffffffff Debug: embeddedice.c:251 embeddedice\_write\_reg(): 12: 0x00000100 Debug: embeddedice.c:251 embeddedice\_write\_reg(): 13: 0x000000f7 Debug: arm7\_9\_common.c:712 arm7\_9\_deassert\_reset(): target-\>state: reset Debug: jtag.c:234 jtag\_call\_event\_callbacks(): jtag event: 2 Debug: jtag.c:1044 jtag\_reset\_callback(): Debug: ftd2xx.c:614 jtagkey\_reset(): trst: 0, srst: 0, high\_output: 0x09, high\_direction: 0x0f Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 **Another Try** **OpenOCD telnet command line** Open On-Chip Debugger > halt requesting target halt… target already halted > resume Target 0 resumed > halt requesting target halt… > **openocd.log** Debug: arm920t.c:291 arm920t\_read\_cp15\_interpreted(): opcode: ee150f30, value: 00000010 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:291 arm920t\_read\_cp15\_interpreted(): opcode: ee160f10, value: fffff7ff Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:291 arm920t\_read\_cp15\_interpreted(): opcode: ee160f30, value: 00000000 Debug: target.c:439 target\_call\_event\_callbacks(): target event 0 Info: server.c:67 add\_connection(): accepted ‘telnet’ connection from 0 Debug: target.c:1201 handle\_halt\_command(): Debug: arm7\_9\_common.c:775 arm7\_9\_halt(): target-\>state: halted Warning: arm7\_9\_common.c:779 arm7\_9\_halt(): target was already halted Debug: target.c:1319 handle\_resume\_command(): Debug: arm7\_9\_common.c:1281 arm7\_9\_resume(): Debug: arm7\_9\_common.c:1082 arm7\_9\_restore\_context(): Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:381 arm920t\_write\_cp15\_interpreted(): opcode: ee050f10, value: 000000ff, address: 00000000 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:381 arm920t\_write\_cp15\_interpreted(): opcode: ee050f30, value: 00000010, address: 00000000 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:381 arm920t\_write\_cp15\_interpreted(): opcode: ee060f10, value: fffff7ff, address: 00000000 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:381 arm920t\_write\_cp15\_interpreted(): opcode: ee060f30, value: 00000000, address: 00000000 Debug: arm7\_9\_common.c:1098 arm7\_9\_restore\_context(): examining User mode Debug: arm7\_9\_common.c:1112 arm7\_9\_restore\_context(): examining dirty reg: r0 Debug: arm7\_9\_common.c:1112 arm7\_9\_restore\_context(): examining dirty reg: pc Debug: arm7\_9\_common.c:1160 arm7\_9\_restore\_context(): writing register 0 of mode User with value 0x8093009c Debug: arm7\_9\_common.c:1098 arm7\_9\_restore\_context(): examining FIQ mode Debug: arm7\_9\_common.c:1112 arm7\_9\_restore\_context(): examining dirty reg: pc Debug: arm7\_9\_common.c:1098 arm7\_9\_restore\_context(): examining IRQ mode Debug: arm7\_9\_common.c:1112 arm7\_9\_restore\_context(): examining dirty reg: pc Debug: arm7\_9\_common.c:1098 arm7\_9\_restore\_context(): examining Supervisor mode Debug: arm7\_9\_common.c:1112 arm7\_9\_restore\_context(): examining dirty reg: pc Debug: arm7\_9\_common.c:1098 arm7\_9\_restore\_context(): examining Abort mode Debug: arm7\_9\_common.c:1112 arm7\_9\_restore\_context(): examining dirty reg: pc Debug: arm7\_9\_common.c:1098 arm7\_9\_restore\_context(): examining Undefined mode Debug: arm7\_9\_common.c:1112 arm7\_9\_restore\_context(): examining dirty reg: pc Debug: arm7\_9\_common.c:1199 arm7\_9\_restore\_context(): writing PC with value 0x00000000 Debug: embeddedice.c:251 embeddedice\_write\_reg(): 0: 0x00000000 Debug: target.c:439 target\_call\_event\_callbacks(): target event 1 Debug: arm7\_9\_common.c:1384 arm7\_9\_resume(): target resumed Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: target.c:1201 handle\_halt\_command(): Debug: arm7\_9\_common.c:775 arm7\_9\_halt(): target-\>state: running Debug: embeddedice.c:251 embeddedice\_write\_reg(): 9: 0xffffffff Debug: embeddedice.c:251 embeddedice\_write\_reg(): 11: 0xffffffff Debug: embeddedice.c:251 embeddedice\_write\_reg(): 12: 0x00000100 Debug: embeddedice.c:251 embeddedice\_write\_reg(): 13: 0x000000f7 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 ---
**Author:** ![tecnologia](https://avatars.discourse-cdn.com/v4/letter/t/bcef8e/32.png) [@tecnologia](https://community.sparkfun.com/u/tecnologia)\ **Post date:** [July 25, 2006, 2:46pm UTC](https://community.sparkfun.com/t/halt-problem/2288/2 "2006-07-25T14:46:07Z")
Using the config below we had some improvements, thou not always we can get control over the board: we altered the: reset\_config trst\_only **arm9\_ftd2xx.cfg** #daemon configuration telnet\_port 4444 gdb\_port 3333 #interface interface ftd2xx ftd2xx\_device\_desc “Amontec JTAGkey A” ftd2xx\_layout “jtagkey” ftd2xx\_vid\_pid 0x0403 0xcff8 jtag\_speed 1 #use combined on interfaces or targets that can’t set TRST/SRST separately **reset\_config trst\_only** #jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) jtag\_device 4 0x1 0xf 0xe #target configuration daemon\_startup halt #target target arm920t little reset\_halt 0 #working\_area 0 0x200000 0x4000 backup #run\_and\_halt\_time 0 30 #flash configuration #flash bank \ \ [driver\_options …] #flash bank cfi 0x10000000 0x800000 2 2 0 ~ ---
**Author:** ![ntfreak](https://avatars.discourse-cdn.com/v4/letter/n/ee7513/32.png) [@ntfreak](https://community.sparkfun.com/u/ntfreak)\ **Post date:** [July 28, 2006, 4:11am UTC](https://community.sparkfun.com/t/halt-problem/2288/3 "2006-07-28T04:11:56Z")
What pins are connected to trst and srst on your target board ? Are these pins connected together, independant, etc ? Openocd can use many combinations of srst and trst but only if your hardware matches what it expects. Cheers Spen ---
**Author:** ![tecnologia](https://avatars.discourse-cdn.com/v4/letter/t/bcef8e/32.png) [@tecnologia](https://community.sparkfun.com/u/tecnologia)\ **Post date:** [July 28, 2006, 11:48am UTC](https://community.sparkfun.com/t/halt-problem/2288/4 "2006-07-28T11:48:45Z")
in the EDB9302 kit board the trst is connected to the trst in the EP9302. The rst is connected to the RSTON pin, which is a reset pin in the EP9302, thou it may be disconnected from that pin via a jumper. In all our tests using the option trst was the one that gave the best results, thou we can debug sometimes it halts and it is necessary to reset the openocd. It seems that we or not in control of the CPU. ---
**Author:** ![Dominic](https://avatars.discourse-cdn.com/v4/letter/d/13edae/32.png) [@Dominic](https://community.sparkfun.com/u/Dominic)\ **Post date:** [July 28, 2006, 12:27pm UTC](https://community.sparkfun.com/t/halt-problem/2288/5 "2006-07-28T12:27:52Z")
Could you please send me full debug output to Dominic.Rath [gmx.de](http://gmx.de)? I suspect there might be a problem with the reset circuitry, but would like to have a look at what happens once the OpenOCD starts up. In general, the option “reset\_config trst\_and\_srst” is the best solution, as it gives you full control over what the processor does. All other options are somewhat limited. Regards, Dominic ---
**Author:** ![tecnologia](https://avatars.discourse-cdn.com/v4/letter/t/bcef8e/32.png) [@tecnologia](https://community.sparkfun.com/u/tecnologia)\ **Post date:** [July 28, 2006, 1:20pm UTC](https://community.sparkfun.com/t/halt-problem/2288/6 "2006-07-28T13:20:22Z")
It was a good hint, because looking at the log I found out that the option daemon\_startup \<‘attach’|‘reset’\> we were using halt, which is a wrong option. If that might be the problem than our problem might be solved. I have returned the board to our distributor and now I will have to wait for our prototype board to be ready so that we can test again to come to a conclusion. **GDB version problem** Another problem that we had during the environment setup was that we were using the GDB 5.3 that came with the Cirrus’s tools chain from their web site, and it didn’t work along the the OpenOCD. When we figure it out we installed the GDB 6.5 and everything went fine. Thanks Dominic. Follows below the start of the log. **openocd.log** Warning: target.c:1242 handle\_daemon\_startup\_command(): invalid daemon\_startup configuration directive: halt Debug: arm920t.c:721 arm920t\_target\_command(): chain\_pos: 0, variant: (null) Debug: jtag.c:1150 jtag\_init(): Debug: ftd2xx.c:887 ftd2xx\_init(): current latency timer: 2 Debug: ftd2xx.c:977 jtagkey\_init(): 80 08 1b Debug: ftd2xx.c:1034 jtagkey\_init(): 82 09 0f Debug: ftd2xx.c:143 ftd2xx\_speed(): 86 01 00 Debug: jtag.c:234 jtag\_call\_event\_callbacks(): jtag event: 1 Debug: jtag.c:1044 jtag\_reset\_callback(): Debug: jtag.c:234 jtag\_call\_event\_callbacks(): jtag event: 1 Debug: jtag.c:1044 jtag\_reset\_callback(): Debug: openocd.c:98 main(): jtag init complete Debug: openocd.c:102 main(): target init complete Debug: openocd.c:106 main(): flash init complete Debug: gdb\_server.c:1093 gdb\_init(): gdb service for target arm920t at port 3333 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: jtag.c:234 jtag\_call\_event\_callbacks(): jtag event: 3 Debug: jtag.c:1044 jtag\_reset\_callback(): Debug: arm7\_9\_common.c:613 arm7\_9\_poll(): DBGACK set, dbg\_state-\>value: 0xd Warning: arm7\_9\_common.c:616 arm7\_9\_poll(): DBGACK set while target was in unknown state. Reset or initialize target before resuming Debug: embeddedice.c:251 embeddedice\_write\_reg(): 0: 0x00000005 Debug: embeddedice.c:251 embeddedice\_write\_reg(): 12: 0x00000000 Debug: arm7\_9\_common.c:907 arm7\_9\_debug\_entry(): target entered debug from ARM state Debug: arm7\_9\_common.c:926 arm7\_9\_debug\_entry(): target entered debug state in Supervisor mode Debug: arm7\_9\_common.c:967 arm7\_9\_debug\_entry(): entered debug state at PC 0x1e274 Debug: arm920t.c:448 arm920t\_post\_debug\_entry(): cp15\_control\_reg: c000107f Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:291 arm920t\_read\_cp15\_interpreted(): opcode: ee150f10, value: 00000005 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:291 arm920t\_read\_cp15\_interpreted(): opcode: ee150f30, value: 00000010 Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:291 arm920t\_read\_cp15\_interpreted(): opcode: ee160f10, value: fffffffc Debug: embeddedice.c:155 embeddedice\_read\_reg\_w\_check(): 1 Debug: arm920t.c:291 arm920t\_read\_cp15\_interpreted(): opcode: ee160f30, value: 00000000 Debug: target.c:439 target\_call\_event\_callbacks(): target event 0