# Reset problem with ST SpearNet **URL:** \ **Category:** MicroMod\ **Tags:** arm-lpc\ **Created:** [March 19, 2007, 9:06pm UTC](https://community.sparkfun.com/t/reset-problem-with-st-spearnet/3933 "2007-03-19T21:06:19Z")\ **Posts on this page:** 2\ **Page:** 1
**Author:** ![FritzBrause](https://avatars.discourse-cdn.com/v4/letter/f/839c29/32.png) [@FritzBrause](https://community.sparkfun.com/u/FritzBrause)\ **Post date:** [March 19, 2007, 9:06pm UTC](https://community.sparkfun.com/t/reset-problem-with-st-spearnet/3933/1 "2007-03-19T21:06:19Z")
Hi, I’m using OpenOCD 1.27 with Amontec JTAGkey tiny and a STEVAL-SPEARNET board from ST Microelectronics with a Spear07NC03 (ARM7 TDMI core). The onboard JTAG connector has TRST connected to the processor, SRST is not connected to anything. The problem is that the core does not get resetted on startup of OpenOCD. My configuration is as follows: - #target configuration The OpenOCD log: - Debug: jtag.c:1192 jtag\_examine\_chain(): JTAG device found: 0x0f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x0 I do not understand the error message, of course the current configuration does not support SRST; how can I get core reset at all if only TRST is connected? Regards, Georg ---
**Author:** ![Dominic](https://avatars.discourse-cdn.com/v4/letter/d/13edae/32.png) [@Dominic](https://community.sparkfun.com/u/Dominic)\ **Post date:** [March 19, 2007, 11:04pm UTC](https://community.sparkfun.com/t/reset-problem-with-st-spearnet/3933/2 "2007-03-19T23:04:21Z")
Without nSRST there’s no way for the OpenOCD to reset the core. nTRST just resets the test logic (JTAG, EmbeddedICE), but leaves the core opreation unaffected. Some cores allow resets to be initiated by writing to a certain register, or by setting up a watchpoint and waiting for it to trigger. If your core supports this you could simply use OpenOCD’s mw[bhw] command to execute a reset. Regards, Dominic