Hi Jim
If neither SYSTICK or another timer is generating interrupts it either means that the global interrupt is masked or that the timers haven’t been set up correctly to generate interrupts.
Check these:
- The SYSTICK configuration (this example is for 50ms from a 96MHz clock)
SYSTICK_RELOAD = 0x00493dff; // set reload value to determine the period
SYSTEM_HANDLER_12_15_PRIORITY_REGISTER |= (SYSTICK_PRIORITY << 24); // enter the SYSTICK priority
SYSTICK_CSR = (SYSTICK_CORE_CLOCK | SYSTICK_ENABLE | SYSTICK_TICKINT); // enable timer and its interrupt - value is 0x00000007
Make sure that the interrupt bit has also been set so that it will also interrupt on reload and not just count.
- Check the PRIMASK in the core registers [CORTEX_M3_REGS.ulPRIMASK] It must be 0. If it is 1, all interrupts are masked.
The vector table configuration looks fine so I don’t think that this has anything to do with the problem.
If you are still convinced that interrupts are occurring there is a simple test; set the vector base address to an invalid area of memory. The NVIC will always try to read the vector from this area and will fail with a hardware access error. Normally this will result in the fault interrupt being called, but is not possible since the fault is due to a vector table access and will fail itself. This will thus set the VECTTBL bit in the Cortex M3 HSFR register, signaling that a fault occurred on attempted NVIC read from the vector table. If you can detect that this bit is being set (the system is also in a crashed state now) it will confirm that an interrupt really occurred since there is no other possibility of setting it.
Regards
Mark