Weird SPI read behaviour

interesting issue… but no real idea… only thoughts

  • Looking at the hal-code… An AM_HAL_IOM_RX is only overturned to AM_HAL_IOM_TX if the number of bytes to read is zero. Could that happen in your code?

  • Not sure what board you have but is there maybe another SPI channel to try.

  • Could the MOSI GPIO be set low somewhere else in the code? E.g. like with CS?

  • Looking at the Artemis datasheet,in chapter 8.2 it talks about SPI flowcontrol, and one possibility is to use MOSI. I don’t see anywhere in the code where that could be set (it is reset during init)

  • Is the TX FIFO not empty from a previous write or maybe still pending 0x0?

  • What is send just before it fails. Say the last bit was zero, is that being repeated with the next read (should not …)

  • Any chance MOSI is pulled low by the SD ?