2 Identical boards, different results?

Development Boards MicroMod
1

I have two identical LPC-H2148 header boards. I am trying to re-program the flash on each one with the exact same cfg, script, and bin files. One seems to re-program just fine(Board #1), while the other (Board #2) is unsuccessful.

I’m using OpenOCD with the Olimex OpenOCD JTAG TINY A device. While running the flash scripts, the most obivous difference to me seems to be that the OpenOCD ‘poll’ command is returning …“current mode: System” for Board #1 and …“current mode: Abort” for Board #2.

Does anyone have any ideas about what might be the issue here (beside my lack of experience ;)? I’ve included the output logs, cfg, and script files below.

Thanks.

patrick

log_ouput file for Board #1 - Successful:
Info: options.c:50 configuration_output_handler(): dcc downloads are disabled

User: target.c:766 target_arch_state(): target state: halted

User: armv4_5.c:340 armv4_5_arch_state(): target halted in ARM state due to debug request, current mode: System

cpsr: 0x800000df pc: 0x00000144

Info: options.c:50 configuration_output_handler(): flash ‘lpc2000’ found at 0x00000000

Info: options.c:50 configuration_output_handler(): erased sectors 0 through 26 on flash bank 0 in 0.156250s

Info: options.c:50 configuration_output_handler(): wrote 744 byte from file main.bin in 0.156250s (4.650000 kb/s)

Warning: arm7_9_common.c:724 arm7_9_poll(): DBGACK set, but the target did not end up in the halted stated 1

Info: options.c:50 configuration_output_handler(): Timed out waiting for reset

log_ouput file for Board #2 - Failed:
Info: options.c:50 configuration_output_handler(): dcc downloads are disabled

User: target.c:766 target_arch_state(): target state: halted

User: armv4_5.c:340 armv4_5_arch_state(): target halted in ARM state due to debug request, current mode: Abort

cpsr: 0x200000d7 pc: 0x0000000c

Info: options.c:50 configuration_output_handler(): flash ‘lpc2000’ found at 0x00000000

Error: armv4_5.c:590 armv4_5_run_algorithm(): timeout waiting for algorithm to complete, trying to halt target

Error: armv4_5.c:590 armv4_5_run_algorithm(): timeout waiting for algorithm to complete, trying to halt target

Warning: lpc2000.c:456 lpc2000_erase(): lpc2000 erase sectors returned 12066728

Error: flash.c:109 flash_driver_erase(): failed erasing sectors 0 to 26

Error: armv4_5.c:590 armv4_5_run_algorithm(): timeout waiting for algorithm to complete, trying to halt target

Error: armv4_5.c:590 armv4_5_run_algorithm(): timeout waiting for algorithm to complete, trying to halt target

Warning: lpc2000.c:603 lpc2000_write(): lpc2000 returned 12067752

Error: flash.c:96 flash_driver_write(): error writing to flash at address 0x00000000 at offset 0x00000000

Warning: arm7_9_common.c:724 arm7_9_poll(): DBGACK set, but the target did not end up in the halted stated 1

Info: options.c:50 configuration_output_handler(): Timed out waiting for reset

//// lpc2xxx_armusbocd_flash.cfg ////

#daemon configuration
telnet_port 4444
gdb_port 3333

#interface
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG TINY A"
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15BA 0x0003
jtag_speed 3 #3
jtag_nsrst_delay 200
jtag_ntrst_delay 200

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst separate #srst_pulls_trst

#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe

#target <type> <startup mode>
#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
target arm7tdmi little run_and_init 0 
run_and_halt_time 0 500

#target configuration
daemon_startup reset

target_script 0 reset openocd_lpc2148_flash.script
working_area 0 0x40000000 0x8000 nobackup

#flash configuration
#flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> ['calc_checksum']
flash bank lpc2000 0x0 0x7D000 0 0 0 lpc2000_v2 12000 calc_checksum

# For more information about the configuration files, take a look at:
# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger

//// openocd_lpc2148_flash.script /////

# The following command will be executed on
# reset (because of run_and_init in the config-file)
# - wait for target halt
# - erase memory
# - reset target and wait for halt
# - flash content of file into target-memory
# - shutdown openocd
#
# created by William Westrick
# referencing OpenOCD wiki documentation
#  http://openfacts.berlios.de/index-en.phtml?title=OpenOCD
# based on information from Martin Thomas 
# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects
# based on information from Dominic Rath 
#

log_output out.txt
arm7_9 dcc_downloads disable #uses slower speeds, but is more reliable?
wait_halt           #wait until halted (waits short time before timing out)
sleep 10            #wait for 10ms
poll                #get device current state
#mdb 0x0 72         #read/display first 72 bytes of memory
flash probe 0       #find blash
flash erase_sector 0 0 26  #erase all flash banks
#mdb 0x0 72         #read/display first 72 bytes of memory
sleep 10            #wait 10ms
reset run_and_halt  #reset the processor and then halt
sleep 100           #wait for 100ms
wait_halt           #wait until halted (waits short time before timing out)
#mdb 0x0 72         #read/display first 72 bytes of memory
flash write_image  main.bin            #write the firmware (can use .bin)
sleep 10            #wait for 10ms
#mdb 0x0 72         #read/display first 72 bytes of memory
reset run           #reset and run the processor
sleep 10            #wait for 10ms
shutdown            #shutdown openocd connection
2

One of the boards is faulty?

Leon

3

Did you fix the problem?

4

legomanww:
Did you fix the problem?

I have not been able to determine what the problem is. I'm as green as they come with microcontrollers. Other than the output from OpenOCD, the only thing I've been able to verify is that the voltage measured at the pins for 3.3V, Vref, and Vbat appear to be the same for both boards.

Is there anything else I can do to at least eliminate or narrow down a possible cause?

5

I would recommend running the commands manually using telnet, to see where it breaks exactly.

if you still have the batch files that came with the script file, then run the debug script and then it will let you connect using telnet:

telnet localhost 4444

then just run the commands in the openocd_lpc2148_flash.script file one at a time

It looks like there is some timing issue, so maybe going slow will let it keep up.

6

I guess the difference is that one of the boards has (faulty) code in its flash, while the other board has an empty flash or good code loaded. The target is allowed to run for some time after the reset, because a LPC2000 locks the JTAG interface right after reset, and reenables it only after a few microseconds.

Make sure the PLLs are disabled on the board that reports abort mode (you’re specifying a CLK of 12000 kHz, i.e. the crystal frequency with no PLLs running). You could also try a “soft_reset_halt” after entering debug mode, to have at least the ARM core initialized to its reset default.

Best regards,

Dominic