4-layer and split planes

I’m working on a board with an FPGA and Gig-E PHY, and following the recommendations on power & ground has resulted in a fairly complex beastie of a board.

It’s got split planes on both power and ground - about 4 splits per plane. I would assume that all four layers can be treated as signal layers, or at least, pour layers. There is the source 5, 3.3V_FPGA, 3.3V_PHY(digital), 3.3V_PHY(analog), 1.5V_FPGA, 1.2V_PHY(digital), and 1.2V_PHY(analog).

I can’t reasonably route this board in 4 layers without the split planes, however, I’m in no hurry, and can afford to wait months if necessary.

Does this seem like a reasonable project for this service?

Thanks!

Probably a bit late for you, but split ground planes are generally frowned on these days (for EMC reasons as much as anything). Some datasheets still have recommendations that are not best-practice.

When you do use split planes, you have to take a lot of care about return paths (and not creating large current loops due to the split). It is normally better to properly segregate analog / digital sections rather than put split planes.

Have a look at this; you have to register (free) but Keith’s advice is well worth it:

http://www.compliance-club.com/KeithArm … artid=4152