I’m working on a board with an FPGA and Gig-E PHY, and following the recommendations on power & ground has resulted in a fairly complex beastie of a board.
It’s got split planes on both power and ground - about 4 splits per plane. I would assume that all four layers can be treated as signal layers, or at least, pour layers. There is the source 5, 3.3V_FPGA, 3.3V_PHY(digital), 3.3V_PHY(analog), 1.5V_FPGA, 1.2V_PHY(digital), and 1.2V_PHY(analog).
I can’t reasonably route this board in 4 layers without the split planes, however, I’m in no hurry, and can afford to wait months if necessary.
Does this seem like a reasonable project for this service?
Thanks!