58.9824 or 53.236800 mhz

Development Boards MicroMod
1

here is script from the GNUARM/Eclipse tutorial

// 				Setting the Phased Lock Loop (PLL)
	//               ----------------------------------
	//
	// Olimex LPC-P2106 has a 14.7456 mhz crystal
	//
	// We'd like the LPC2106 to run at 53.2368 mhz (has to be an even multiple of crystal)
	// 
	// According to the Philips LPC2106 manual:   M = cclk / Fosc	where:	M    = PLL multiplier (bits 0-4 of PLLCFG)
	//																		cclk = 53236800 hz
	//																		Fosc = 14745600 hz
	//
	// Solving:	M = 53236800 / 14745600 = 3.6103515625
	//			M = 4 (round up)
	//
	//			Note: M - 1 must be entered into bits 0-4 of PLLCFG (assign 3 to these bits)
	//
	//
	// The Current Controlled Oscilator (CCO) must operate in the range 156 mhz to 320 mhz
	//
	// According to the Philips LPC2106 manual:	Fcco = cclk * 2 * P    where:	Fcco = CCO frequency 
	//																			cclk = 53236800 hz
	//																			P = PLL divisor (bits 5-6 of PLLCFG)
	//
	// Solving:	Fcco = 53236800 * 2 * P
	//			P = 2  (trial value)
	//			Fcco = 53236800 * 2 * 2
	//			Fcc0 = 212947200 hz    (good choice for P since it's within the 156 mhz to 320 mhz range
	//

I dont understand how we can get the LPC2106 running at 53.2368 mhz as it is not even multiple of 14.7456 mhz. with the PLLCFG set to 0x23, shouldnt the LPC2106 run at 58.9824 mhz.

pls help

2

Hi Teekay.

The annotation is incorrect and you are right. I apologise that this error crept into the tutorial and will correct it in the next revision. The section should be revised as follows:

// Setting the Phased Lock Loop (PLL)

// ----------------------------------

//

// Olimex LPC-P2106 has a 14.7456 mhz crystal

//

// We’d like the LPC2106 to run at 58.982400 mhz (has to be an even multiple of crystal)

//

// According to the Philips LPC2106 manual: M = cclk / Fosc where: M = PLL multiplier (bits 0-4 of PLLCFG)

// cclk = 58982400hz

// Fosc = 14745600 hz

//

// Solving: M = 58982400/ 14745600 = 4

//

// Note: M - 1 must be entered into bits 0-4 of PLLCFG (assign 3 to these bits)

//

//

// The Current Controlled Oscilator (CCO) must operate in the range 156 mhz to 320 mhz

//

// According to the Philips LPC2106 manual: Fcco = cclk * 2 * P where: Fcco = CCO frequency

// cclk = 53236800 hz

// P = PLL divisor (bits 5-6 of PLLCFG)

//

// Solving: Fcco = 58982400* 2 * P

// P = 2 (trial value)

// Fcco = 58982400 * 2 * 2

// Fcc0 = 235929600hz (good choice for P since it’s within the 156 mhz to 320 mhz range

//

// From Table 19 (page 48) of Philips LPC2106 manual P = 2, PLLCFG bits 5-6 = 1 (assign 1 to these bits)

//

// Finally: PLLCFG = 0 01 00011 = 0x23

//

// Final note: to load PLLCFG register, we must use the 0xAA followed 0x55 write sequence to the PLLFEED register

// this is done in the short function feed() below

//

Thanks for pointing this out, Teekay. The PLL register settings were OK but the CPU was actually running at 58.982400 mhz as you observed. The purpose of the tutorial was to teach how to assemble an Open Source cross development system. However, I should have paid more attention to ancillary issues like this.

Cheers,

Jim Lynch