I have 4 devices in my design that require clocks/crystals. Three of them can use crystals, but one requires a clock. Rather than place 3 crystals (and their associated capacitors) and generate the clock the the final device, I want to use a clock oscillator. What is unclear to me though, is what the fanout of these clock oscillators are. Looking at the datasheets, they don’t mention drive strength. Do I need clock buffers? Do I need a fanout device? Or can I safely drive all 4 devices with a single device?
I vaguely recall something about CL an indicator of the maximum load. This part mentions a CL of 15pF. Does that mean it can drive 15pF of load? If my devices each have 5pF of input capacitance, I need at least a 20pF CL device (+ some for trace capacitance)?
I’m not worried about skew (the devices that do communicate can do so asynchronously). But I am worried about slow rise/fall times and jitter. Also, one of the devices is a USB peripheral, so the clock needs to be fairly clean.
The load capacitance gives you the feedback capacitor value in the usual Pierce oscillator circuit. It should be around 2*Cl, allowing for stray capacitance.
leon_heller:
The load capacitance gives you the feedback capacitor value in the usual Pierce oscillator circuit. It should be around 2*Cl, allowing for stray capacitance.
Thanks for the info. I'm still a bit unclear as to what Cl I should specify. When you say "should be around 2*Cl", do you mean the Cl for the part should be about 2 times the load? So if driving 4 inputs, each with 5pF input capacitance, I should get a part with a Cl of 40pF (4 * 5pF = 20pF load, times 2, or 40pF)?
No. If you are using it in an on-chip oscillator and the crystal load capacitance is 15 pF, two 27 pF feedback capacitors would probably be about right. They are effectively in series, in the usual Pierce configuration.
leon_heller:
No. If you are using it in an on-chip oscillator and the crystal load capacitance is 15 pF, two 27 pF feedback capacitors would probably be about right. They are effectively in series, in the usual Pierce configuration.
Ok, I think I've been a bit unclear. I'm not talking a crystal, but an oscillator. One with VDD/VSS and an enable/tristate and a clock output. It generates a clock signal directly, and doesn't need a crystal or load capacitors (other than a bypass cap between VDD/VSS).
How do I determine the drive of the clock output? Can I drive multiple clock inputs? Or is it anticipated that a clock driver/fanout/distribution device is used?
leon_heller:
It should be part of the oscillator specification.
That's what I'm trying to figure out. The oscillator I posted doesn't say what the fanout or drive is for the device. The closest things it says is "Output load". Do they mean this is the load of their own pin? Or the maximum load it can drive?
Assuming all four of the devices you’re driving have regular CMOS clock inputs, you should be fine with that oscillator.
On your PCB, connect the clock output to four separate 33R resistors, and then route from the other end of each resistor to one individual load. The resistors should be physically located as close to the oscillator module as you can reasonably get them.
AndyC_772:
Assuming all four of the devices you’re driving have regular CMOS clock inputs, you should be fine with that oscillator.
On your PCB, connect the clock output to four separate 33R resistors, and then route from the other end of each resistor to one individual load. The resistors should be physically located as close to the oscillator module as you can reasonably get them.
Thanks. Especially with regard to the termination resistors.
For future reference, how do you know that this part is fine? If I want to pick a different oscillator, what parameters should I look at?
It’s a bit tricky to explain what to look for, because the manufacturer of the oscillator doesn’t really have all the answers. The maximum capacitance that it can drive depends not only on the oscillator itself, but also on what constitutes an acceptable signal at the input of the receiving device.
The oscillator’s data sheet might say (for example) that it can drive a maximum of 20pF and that it has a rise time of 2ns - ie. it takes that amount of time to go from a well-defined logic ‘0’ to ‘1’ or back again.
If your load (ie. the sum total of all the capacitance due to the devices you’re driving and the traces on your PCB) is, say, 30pF, then the oscillator will almost certainly still work OK, but the rise time will be a bit slower.
Whether or not that’s a problem depends on many things. Some devices have a minimum slew rate which must be achieved in order to guarantee reliable switching. Others specify a maximum slew rate which must not be exceeded. On a noisy board, there’s a risk that the input to a device will see multiple transitions if the level stays around the 0-1 threshold voltage for too long, because the added noise will push it just over the threshold and back again.
When I say ‘you should be fine’, I have to be honest and admit it’s more a of a gut reaction based on a great deal of experience with using this type of device, rather than a strict calculation. It is possible to conduct detailed simulations of designs to “prove” that they will “definitely” work - and I put these terms in quotes because no simulation is perfect either - but that’s the realm of professional signal integrity experts with access to hugely expensive, specialist software. I’ve done that stuff myself for particularly demanding designs, but more often than not I’ll build a prototype and then check it over with a good quality oscillscope if I have any doubts about a particular part of the board.
