Hi Folks,
I’ve been looking into how i can debug a lpc 1343 board using OpenOCD , I’ve come across a config script that goes in the tcl\target directory
also next question i’m using a st-link v2 , so to run openOCD , is this the correct command
openocd -f interface/stlink-v2.cfg -f board/lpc1343.cfg
the file is as below ( called lpc1343.cfg)
NXP LPC1343 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM,
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1343
}
After reset the chip is clocked by the 12MHz internal RC oscillator.
When board-specific code (reset-init handler or device firmware)
configures another oscillator and/or PLL0, set CCLK to match; if
you don’t, then flash erase and write operations may misbehave.
(The ROM code doing those updates cares about core clock speed…)
CCLK is the core clock frequency in KHz
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
set _CCLK 12000
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200
reset_config trst_and_srst
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
LPC1341 has 8kB of SRAM In the ARMv7-M “Code” area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x2000
LPC1341 has 32kB of flash memory, managed by ROM code (including a
boot loader which verifies the flash exception table’s checksum).
flash bank lpc2000 0 0 <target#> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
#flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 $_CCLK calc_checksum
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 120000
LPC13xx has only SWD mode.
swd_mode 2
swd_delay 0
$_TARGETNAME configure -event reset-init {
Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
“User Flash Mode” where interrupt vectors are not remapped,
and reside in flash instead).
See Table 6. System memory remap register (SYSMEMREMAP - 0x4004 8000) bit description
1:0 MAP System memory remap (default:10)
00 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
01 User RAM Mode. Interrupt vectors are re-mapped to StaticRAM.
10 or
11 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
31:2 Reserved (default:00)
http://ics.nxp.com/support/documents/mi … &type=user
mww 0x40048000 0x02
}
proc mt_internal_rc {} {
#Currentry not PLLED yet
halt
sleep 10
flash probe 0
}
proc mt_internal_rc_ex {} {
#Currentry not PLLED yet
halt
sleep 10
flash probe 0
}
proc mt_flash {IMGFILE} {
mt_internal_rc
flash write_image erase $IMGFILE
sleep 10
verify_image $IMGFILE
sleep 10
soft_reset_halt
resume
shutdown
}
proc eraser {} {
mt_internal_rc
sleep 10
flash erase_sector 0 0 7
sleep 10
flash erase_check 0
sleep 10
soft_reset_halt
shutdown
}
#debug_level 3
init
#reset init
Kind Regards
Justin
ps is this is the right config for the NXP 1343 can i get added to the svn for this project ?