I cannot probe the flash for the combination CS-E9302, ARM-USB-OCD and openocd.
When I probe I get this error:
halt
requesting target halt…
Target 0 halted
target halted in ARM state due to debug request, current mode: IRQ
cpsr: 0x60000092 pc: 0xffff0018
MMU: enabled, D-Cache: enabled, I-Cache: enabled
flash probe 0
probing failed for flash bank ‘#0’ at 0x60000000
openocd reports the following:
Info: openocd.c:86 main(): Open On-Chip Debugger (2007-04-26 16:40 CEST)
Warning: arm7_9_common.c:2009 arm7_9_write_memory(): memory write caused data abort (address: 0x60000aaa, size: 0x2, count: 0x1)
and a lot of similar lines.
part of my config file:
jtag_speed 1
reset_config trst_and_srst
target arm920t little reset_halt 0
working_area 0 0x80014000 0x1000 backup
flash bank cfi 0x60000000 0x1000000 2 2 0
Has anyone got this setup working ?
Thanks
Per
Hi,
you are running with the MMU enabled, apparently while executing an IRQ handler. At this point, the flash is most likely not mapped to 0x60000000, and caching might be enabled at the location where it is mapped.
To flash using the OpenOCD please issue a “reset halt” while your target is running. This allows you to debug your system out of reset. Either allow your bootloader to configure the clocks and memories, or use a script to perform this yourself, like I do in http://mmd.ath.cx/openocd/cfgs/cs_ep9301_init.script. While these timings are for the 166/66 MHz EP9301 they should work for your EP9302, too.
After running this script you should be able to write to your flash at 0x60000000 without problems.
Regards,
Dominic
Hi Dominic,
thanks for replying
I just discovered my problem was in the ARM-USB-OCD hardware. By replacing the R25 resistor with a new one it works perfect. I can poll the flash using your supplied script.
I found the jtag reset pin (15) did not react on commands from openocd. I could see the reset signal on the FT2232 chip. To my astonishment the problem wasnot the Q4 transistor driving the jtag reset, but the resistor driving Q4 !
I still have some learning to do, before I dare to reflash the redboot SW.
Per