I’ve been using caps mostly as rules-of-thumb and whatever’s been recommended by the manufacturer via the datasheet.
I’ve been using:
~0.1uF ceramic (or tantalum) cap near any IC (microcontrollers and op-amps mostly) to respond to high-frequency demands
~10uF tantalum cap
~100uF electrolytic cap at the board level (near however the board is getting power)
I’m trying to simplify a low-cost project by removing the capacitor near the power and gnd pins of the microcontroller, but am not sure what I’ll be losing. Is there a way to quantify the loss in performance or better understand any risk I might take on without that cap? What might be at risk should I not include that 0.1uF cap near the power rails of my microcontroller?
I’d like to better understand the effect of that cap, but any relevant experience is much appreciated too: Will I be OK without that cap for a simple battery-powered project using an MCU running at 8MHz and sampling for A/D conversion at 500kHz?
Decoupling capacitors are essential for reliable operation. Google for more information.
The simplest explanation I can give is this…
You’re power supply has an frequency dependent output impedance which causes the output voltage to look like a low-pass filter if plotted in the frequency domain. Sometimes the bandwidth is specified for your power supply (more so if you’re using a linear regulator) but more often than not, this information is unavailable.
Decoupling capacitors help to extend the bandwidth of the power supply, effectively lowering the power supply output impedance over certain frequency range depending on the package size and value of the capacitor. The power supply load (aka your microcontroller) will have some equivalent impedance and forms a voltage divider with the power supply. If you don’t have the decoupling capacitors then up at the frequencies associated with the higher-speed switching of your microcontroller, the power supply output impedance may be so high that it could actually reset the microcontroller and anything else on that power supply rail. There could be a whole host of other problems that could arise as well depending on your circuit.
When I design or evaluate a decoupling network I always start by determining a target output impedance over a target bandwidth. For example, I may find that I can tolerate 100 mV of power supply droop for a 3.3V supply. I also determine that my worst case load draws 50 mA. The target impedance is then 100mV/50mA=2ohms. The bandwidth however is proportional to the fastest edge rate in your design. For an 8 MHz signal, I might guess that the edge rise time is 10% of the period or 0.1/8MHz=12.5ns. I’m using a guess here because for an 8 MHz microcontroller, there is not likely any application information from the manufacturer for decoupling since this is pretty slow. The bandwidth of a 12.5ns rise time can be calculated using BW=0.34/12.5ns=27.2MHz, this is the decoupling network bandwidth design target. There are several variations to the bandwidth formula I used there, the one I used models a Gaussian system and I’ll leave it at that.
Now that the two design parameters have been determined I would now jump into some simulation software like [Kemet Spice and try out some different capacitor values out till I get something appropriate. My goal in the simulation is to find a network with an impedance of less than 2 ohms over my target bandwidth of 27.2 MHz, I will also ignore lower frequencies as long as I know the power supply can handle those. Its difficult to dive into this subject without writing a long story so I’ll stop here and let you do some playing but hopefully this gives you some foundation to work on.](http://www.kemet.com/page/kemsoft)
wow, thank you for the thoughtful response rrpilot.
