robodude666:
Have you been able to estimate how many FPS you can get out of that FPGA with full screen coloring?
Whatever the maximum refresh rate of the screen is will be your limitation, not the FPGA. Spartan 3E devices can handle full 1080P resolutions at well over 60Hz without breaking a sweat.
Now that I’ve read over the datasheet of the display, I was wondering how you got 30FPS as the limit.
If you go by the nominal clocking rate of 9MHz you get just shy of 60fps: 9MHz/525/286=59.94fps (includes front/back porch and setup pulse).
Or did you go by the nominal response time of the screen at 30ms which is about 33fps?
The good news for everyone that is new to FPGA’s is the PSP screen is driven in the same manner as a VGA monitor and there are lots of VHDL and Verilog examples on the net to help you along. Implementing a memory controller, hardware sprite generator, and microcontroller interface will be the fun part!
Yes, the PSP LCD can be used with an ARM processor, but must have an internal display controller. Unfortunately all processors with display controller I’ve ever seen are in BGA packages (including the i.MX21)…
Thanks for all the info! I would love to use the i.MX21 but it is in a BGA package. I only know how to solder Hole-Thru components… Plan to make some BatchPCB SMD board orders to learn QFP and the other fun SMD packages…
Would the PSP LCD be able to run off of a LPC for example? Or does it need a i.MX21/FPGA? How well could it run off of a dsPIC?
I’ve looked at the fpga4fun site a bit more and there is a lot of fun stuff there, sadly I can’t get my head to wrap around this HDL business yet. I think I would want to learn AVG + ARM stuff and ASM before moving onto HDL + FPGAs. I also love PICs ='[.
With some creative hardware design, a 30 or 40MIPS dsPIC could maintain the minimum scan rate of the LCD but that is pretty much all it would be doing. The only free time for processing would be during the 14 lines that are part of the vertical back and front porch which doesn’t amount to much. You would end up having to use a dual port SRAM and have one dsPIC dedicated to driving the LCD while the other one would be your normal embedded system.
Off hand I don’t know the instruction rate of LPCs but I’m sure it would have the same issues as the dsPIC.
The main problem is Microcontrollers are not designed to handle very high speed repetitive loops where FPGAs excel at it due to their architecture.
Well… I am currently using the OLED from SF and I plan to get a dedicated dsPIC/PIC to drive it and then do a master/slave I2C communication between my OLED PIC and my main “brain” PIC.
What would the LPC require to control this LCD and a touchscreen at a high rate? Currently, driving the OLED via bitbang SPI (i’ll move it to 9-bit parallel soon) it takes a few seconds for text to be drawn. I want it done instantly.
Any LPC micro will draw instantly text on the OLED display, and still have lots of cpu idle time to do other things, especially if using interrupts. Probably if reading from the display is not required using hardware (not bitbanged) SPI will be nearly as fast as parallel interface.
About driving directly the PSP LCD things are much worse, even if the cpu runs @ 60MHz the output pin can be driven at a maximum frequency of 4MHz, and that is about half the frequency needed to drive the LCD
Even if new devices, that have the /01 suffix, like LPC2106/01 have outputs capable of running @ 13MHz, even writing the code in assembly won’t allow to output data correctly. Also the maximum amount of internal ram is 64KB for these devices, far less than what is required for a full image.
I think the only way to drive the display is to use a CPLD/FPGA+external ram as framebuffer to interface the LCD with an mcu. Or use an mcu with display driver, but they’re BGA…
Yes, I believe that there’s a way to use that LCD without buying the virtualcogs board. Anyway, my first problem is that I know nothing of VHDL and verilog… That’s why at the beginning I was thinking at something like an i.MX21 chip, but I soon realized that soldering a BGA is impossible, and there’s also the problem of drawing the pcb, since it must be 4 or 6 layers to route properly a BGA…
So I decided to learn verilog
I hope a CPLD will be enough to make a simple framebuffer with microcontroller interface, and then it’s possible to use an ARM or AVR to drive it
You use masking tape to lock the chip in place, then rub solder on the back and the chip is then soldered into place. You then use break away headers to access the pins! I am considering getting a few if I can find some good “getting started with i.MX21” sites.
Making a PCB would be a much cheaper option I think though =/
inventore123:
I hope a CPLD will be enough to make a simple framebuffer with microcontroller interface, and then it’s possible to use an ARM or AVR to drive it
A decent CPLD should be large enough to handle a simple memory interface and display logic. What you can do is download the free development tools from Xilinx and Altera and try working on your design. Once you synthesize it you will be able to tell what parts your design will fit in.
For Xilinx you would download ISE WebPACK
For Altera you would download Quartus II Web Edition
There are a lot of sites on the internet with tutorials in VHDL and Verilog. I use VHDL because that is what I learned in the beginning. I’ve never really sat down and played with Verilog.
phalanx:
For Xilinx you would download ISE WebPACK
For Altera you would download Quartus II Web Edition
I just installed and updated the [[Xilinx](http://www.xilinx.com) WebPack and am downloading the [[Altera](http://www.altera.com) Quartus and ModelSim free packages now. I also got the free 1 year Libero Gold from [[Actel](http://www.actel.com). This should cover all the biggies. :)
phalanx:
There are a lot of sites on the internet with tutorials in VHDL and Verilog. I use VHDL because that is what I learned in the beginning. I’ve never really sat down and played with Verilog.
My friend, robodude, pointed me at [[FPGA 4 FUN](http://www.fpga4fun.com), which looks very cool and interesting.
Well, theoretically it could be done, but I think there are still 2 problems:
-since the schmartboard is a breakout board you still need to solder 400 wires :shock: to it, to connect every pin of the i.MX21 to the other devices…
-all that wires will likely cause a lot of signal integrity issues because the i.MX21 runs @ 200+MHz
A decent CPLD should be large enough to handle a simple memory interface and display logic.
finally a good news, thanks phalanx :D
I’ve already installed ISE Webpack for linux, can someone suggest a good (and cheap) programmer for xilinx devices, that works on linux? or maybe just a schematic, if it isn’t too complex?