When I compile with gcc, the compiler generates the table of exception vectors, but I note that the LSB is always set. The address contained in the vector is always the actual handler address +1. The code works, however, because the STM32 uses 16-bit instructions and forces instructions to load on half-word boundaries.
Why are the vectors as compiled off by 1? Should I worry about this?
Regards,
Peter
I’m not familiar with the STM32 yet, but IIRC generally branching to an odd address (bit0 of the PC is 1) is used to change state from ARM to thumb mode.
No need to worry about it.
The LSb=1 in the PC selects the THUMB2 instruction set. If you try to load an address with LSb=0 into the PC then the core would generate an exception because the Cortex-M3 is not able to execute normal ARM code.
The real address has the bit masked to 0, so as example, if you read 0x10001 the real address is 0x10000 and the execution mode is THUMB2.
regards,
Giovanni
Thank you, gdisirio. More than not worrying about it, I now understand it.
Understanding is everything. I hate “magic”.
Thanks again,
Peter