flashing Sam7A3, lock error bit problem

pgasper · October 2, 2006, 6:07pm

I am programming flash memory on my AT91Sam7A3. The A3 is a 256KB (1024 pages of 256bytes), single flash bank device with 16 lock bits of 4kb each (16 pages of 256 bytes each). So only the bottom 64 KB is protected.

I am using WinArm and openocd-2006re80

I am unable to succcessfully program above a certain code size.

This compile works:

Size after:

main.elf :

section size addr

.text 9476 0

.data 4 2097152

.bss 2728 2097156

.comment 1728 0

.debug_aranges 1936 0

.debug_pubnames 3140 0

.debug_info 32760 0

.debug_abbrev 4748 0

.debug_line 7540 0

.debug_frame 4168 0

.debug_str 691 0

.debug_loc 4914 0

Total 73833

This compile doesn’t:

Size before:

main.elf :

section size addr

.text 16340 0

.data 4 2097152

.bss 2732 2097156

.comment 1728 0

.debug_aranges 1936 0

.debug_pubnames 3140 0

.debug_info 32760 0

.debug_abbrev 4748 0

.debug_line 7541 0

.debug_frame 4168 0

.debug_str 691 0

.debug_loc 4914 0

Total 80702

Open On-Chip Debugger
> flash info 0
#1: at91sam7 at 0x00000000, size 0x00000000, buswidth 0, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 16kHz
pagesize: 256, lockbits: 16 0xeee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> exit

It seems some lock bits are still set; but I am unable to clear them.

> flash protect 0 0 15 off
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 16kHz
pagesize: 256, lockbits: 16 0xeee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

>

Dominic · October 2, 2006, 6:16pm

First of all you should upgrade to a recent version of the OpenOCD, currently there’s re100rc01 available from Michael Fischer’s yagarto.de page.

If the problem exists in the current code, too, I’ll have a look at the SAM7A datasheets to see what might cause problem.

Regards,

Dominic

pgasper · October 2, 2006, 6:19pm

I’ll do that.

BTW, the error I got when loading code was:

Programming with OPENOCD
C:\Program Files\openocd-2006re80\bin\openocd-pp.exe -f oocd_sam7_flash.cfg
Info:    openocd.c:82 main(): Open On-Chip Debugger (2006-08-01 12:00 CEST)
Warning: arm7_9_common.c:675 arm7_9_assert_reset(): srst resets test logic, too
Info:    target.c:216 target_init_handler(): executing reset script 'oocd_sam7_flash.script'
Error:   at91sam7.c:247 at91sam7_wait_status_busy(): status register: 0xeee80005
Error:   at91sam7.c:249 at91sam7_wait_status_busy(): Lock Error Bit Detected, Operation Abort

pgasper · October 2, 2006, 6:28pm

nope, same behavior under the newest.

mlu · October 2, 2006, 7:01pm

AT91Sam7A3 usues different bit in the flash status register MC_FSR to

signal that a lock bit change has completed.

So the current code, tested on 7S and 7X does not properly wait for unlocking to complete

on th SAM7A3.

You can try to unlock one lockbit at a time, this will introduce enough waiting times for the unlocking to complete before next flash command arrives.

If this works then we know the problem and can fix the protect/unprotect protocol for the 7A3 .

Regards

Magnus

pgasper · October 2, 2006, 7:41pm

I tried it manually a couple times with no luck. Once I was able to set and then clear LOCKS0. But even then I didn’t realize it because the mdw cmd didn’t report the difference till I cycled power. Am I misunderstanding how this procedure should work?

Open On-Chip Debugger
> mdw 0xffffff68 1
0xffffff68: eee80000
> mww 0xffffff64 0x5a00000104
> mdw 0xffffff68 1
0xffffff68: eee80008
> mdw 0xffffff68 1
0xffffff68: eee80000
> mww 0xffffff64 0x5a000104
> mdw 0xffffff68 1
0xffffff68: eee80002
> mww 0xffffff64 0x5a000204
> mww 0xffffff64 0x5a000404
> mww 0xffffff64 0x5a000804
> mww 0xffffff64 0x5a001004
> mww 0xffffff64 0x5a002004
> mww 0xffffff64 0x5a004004
> mww 0xffffff64 0x5a008004
> mww 0xffffff64 0x5a010004
> mww 0xffffff64 0x5a020004
> mdw 0xffffff68 1
0xffffff68: eee80002
> mww 0xffffff64 0x5a000804
> mdw 0xffffff68 1
0xffffff68: eee80002
> mww 0xffffff64 0x5a000804
> mdw 0xffffff68 1
0xffffff68: eee80002
> mdw 0xffffff68 1
0xffffff68: eee80000
>

pgasper · October 2, 2006, 7:47pm

I think I should be getting a reply of eee80004, but that never happened.

OK, I see the issue; I didn’t setup FMCN.

mlu · October 2, 2006, 7:58pm

I think the page number must be 64*lock bit number since there are

64 pages per lock region.

Try unlocking one page at a time with the openoch command:

flash protect 0 3 3 off

flash info

flash protect 0 4 4 off

flash info

etc.

/Magnus

mlu · October 2, 2006, 8:06pm

You are right 16 pages per lock region. Error in the flash info code !

pgasper · October 2, 2006, 8:11pm

well, I don’t have the manual command figured out yet; but look at this flash protect behavior.

Open On-Chip Debugger
> flash info 0
#1: at91sam7 at 0x00000000, size 0x00000000, buswidth 0, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xeee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 0 0 on
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xeee9, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 0 0 off
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xeee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 1 1 off
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xeee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 1 1 on
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xeef8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 1 1 off
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xeee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 2 2 on
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xefe8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 2 2 on
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xefe8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 2 2 off
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xeee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 3 3 on
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xfee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

> flash protect 0 3 3 off
> flash info 0
#1: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0

at91sam7 information:
cidr: 0x260a0941, arch: 0x0060, eproc: ARM7TDMI, version:0x001,  flashsize: 0x00
040000
master clock(estimated): 48209kHz
pagesize: 256, lockbits: 16 0xeee8, pages in lock region: 64
securitybit: 0, nvmbits: 0x0

>

mlu · October 2, 2006, 8:21pm

Very good

The lock region that is changed is multiplied by 4, that is because of the error

in the code which uses 64 pages per flash region instead of 16.

So now you can (hopefully) unlock a page by

mww 0xffffff64 0x5a00n004

(PAGEN is 16*n)

/Magnus

pgasper · October 2, 2006, 8:37pm

Yep, that worked (n being 0 - F). And that fixed my flash programming problem.

Of note to anyone who does this mannually is that this method was a little squirrly untill I got the FMCN setup correctly.

Thanks for all the help!

mlu · October 2, 2006, 8:41pm

This was the first reported use of an AT91SAM7A3 so now

I can write a patch (in a few days time) to correct those problems.

Greetings

Magnus

exelty · October 16, 2006, 12:22pm

I am having trouble with the script for the programming the AT91SAM7A3 with a standard LPT wiggler.

Can someone please post me a working script (with changes to fix above) for the current version (r100-rc01)? :roll:

Thanks in advance, really apreciate it.

pgasper · October 16, 2006, 1:31pm

download the newest OpenOCD for the fix.

this is my script:

#daemon configuration
telnet_port 4444
gdb_port 3333

#interface
interface parport
parport_port 0x378
parport_cable wiggler
jtag_speed 0
#use combined on interfaces or targets that can't set TRST/SRST separately
#works well, except resetting
reset_config trst_and_srst srst_pulls_trst 

#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe

#target configuration
daemon_startup reset
#target <type> <startup mode>
#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
#target arm7tdmi little run_and_halt 0 arm7tdmi

target arm7tdmi little run_and_halt 0
#target arm7tdmi little reset_run 0

#target_script 0 reset h2294_init.script
run_and_halt_time 0 30
#working_area 0 0x40000000 0x40000 nobackup

#flash configuration
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
flash bank at91sam7 0 0 0 0 0

exelty · December 1, 2006, 11:28am

I finally got around to trying this script and I still need some more hints.

It seems to initialise our wiggler (its the one from the openocd manual)and reset the processor, however the script seems to stop after the reset command.

so the final line of the debug output is similar to:

...
Info:    configuration.c:50 configuration_output_handler(): requesting target halt... 
Warning: arm7_9_common.c:842 arm7_9_halt(): target was already halted

I added the following line into the script from above;

target_script 0 reset openocd_at91sam7a3_flash.script

where the script is as in;

http://www.siwawi.arubi.uni-kl.de/avr_p … index.html (meant for at91sam7s…)

ie openocd_at91sam7a3_flash.script is:

# 
# The following commands will be executed on
# reset (because of run_and_init in the config-file)
# - halt target
# - init ecr
# - flash content of file main.bin into target-memory
# - shutdown openocd
#
# created by Martin Thomas 
# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects
# based on information from Dominic Rath 
#

halt
sleep 10

# Init - taken form the script openocd_at91sam7_ecr.script 
mww 0xfffffd44 0x00008000	# disable watchdog
mww 0xfffffd08 0xa5000001	# enable user reset
mww 0xfffffc20 0x00000601	# CKGR_MOR : enable the main oscillator
sleep 10
mww 0xfffffc2c 0x00481c0e 	# CKGR_PLLR: 96.1097 MHz
sleep 10
mww 0xfffffc30 0x00000007	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
sleep 10
mww 0xffffff60 0x003c0100	# MC_FMR: flash mode (FWS=1,FMCN=60)
# arm7_9 force_hw_bkpts enable	# program resides in flash

# AT91SAM7 flash command-"batch"
# adapted by Martin Thomas based on information from Dominic Rath - Thanks
arm7_9 dcc_downloads enable
sleep 10
poll
flash probe 0
flash write 0 main.bin 0x0
reset run
sleep 10
shutdown

Anyone see an obvious problem here? or maybe has a proven sam7a3 specific flash programming script complete?(sorry, should have been more specific in last post)

Thanks in advance.

exelty · December 4, 2006, 8:09am

I had another go at this and did find that the reset command used in pgasper’s post didn’t work (since the program occurs on the init event). IE i changed the line:

from

target arm7tdmi little run_and_halt 0

to

target arm7tdmi little run_and_init 0

and it worked! I got the “write complete of main.bin” message.

However, the code did not work as expected, I have a short code to flash a LED but it didnt flash.

The code I used was a simplified version of the AT91SAM7S code from:

http://www.siwawi.arubi.uni-kl.de/avr_p … index.html

Can someone help me out, are there some SAM7A3 specific device initialisations that are required???

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