(HCF4017BE) DECADE COUNTER WITH 10 DECODED OUTPUTS

Look up the attached data sheet.

http://www.scribd.com/doc/27482245

I have suffered one displeasing feature (most times useful) of this counter,

When the clock advances, decade counting also advances from 0 to 9 then 0 to 9 and so on.

That is at first LOW-to-HIGH clock edge “0” out is on, at second LOW-to-HIGH clock edge “1”

out is on, and so on. On reaching “9” again returns to “0” and so on.

Assume we manually switch off the counter supply at seventh LOW-to-HIGH clock edge “8” out is on.

But the problem is that when we power up the circuit again, the counter starts from out “9” not from

initial “0” when detecting first LOW-to-HIGH clock edge.

In most applications this is a good feature.

But look up other attachment.

http://www.scribd.com/doc/27482318

Here I set up a telephone ring detector to turn on off-hook relay

for 60 sec (by 555 mono), when 4017 detects 5th ring as Clock input. That is five LOW-to-HIGH clock (ring)

edges detected, then when goes to “6” out the counter automatically reset by the arrangement shown in schematic.

All these are done to count exactly 5 rings.

These arrangements normally working fine. But what happened when someone wouldn’t complete 5 rings (missed call) ?

That is before completing 5 rings he deliberately cut his phone. Let us assume he disconnect his phone on 2nd ring.

Upon this condition when he tries to redial and want to turn on relay on 5 rings, relay will turn on before 5 rings

that is on 3rd ring. This occurs because of the property of 4017 by which it keeps track of all past (before power up also)

activities.

Is there any counters exist that has no past tracking feature. If I would get such a counter I will add one relay

at the output of opto-coupler, which will close power up connection of my counter when first ring signal occurs.

Thus the counter starts in a fresh mood to count exact no.of rings.

All suggestions are hearty welcoming …

That chip has no memory, so it doesn’t remember where it was when power is removed. It is, however, a CMOS chip with very low current draw and runs on quite low voltages. I’m guessing you aren’t removing power for long enough, and the bypass or filter caps keep things running.

If you really want to force a reset on every power cycle, tie a reset generator chip (or the usual arrangement of a resistor/cap/diode) to the reset pin of the 4017.

/mike

n1ist:
That chip has no memory, so it doesn’t remember where it was when power is removed. It is, however, a CMOS chip with very low current draw and runs on quite low voltages. I’m guessing you aren’t removing power for long enough, and the bypass or filter caps keep things running.

If you really want to force a reset on every power cycle, tie a reset generator chip (or the usual arrangement of a resistor/cap/diode) to the reset pin of the 4017.

/mike

Thanks everyone to bring attention to my problem * (hcf4017be) decade counter with 10 decoded outputs

  • .All suggestions are very valuable.

See my attached link ‘4017’ in first post.

Where I have made a slight change to fulfill my requirement ( I think this would be a simpler version than

all circuits presented by others here).

See the attachment in this last thread.

http://www.scribd.com/doc/27554218

1.5 SEC is designed by R and C of 4093 to satisfy one telephone ringing interval. 74123 retriggerable mono shot is used here.

So Quasi length (0.33RC) of 74123 is selected a little higher than the sum of 1.5 & 1 sec.

Whenever there is no rings at input, Q/ output is logic HIGH which will reset 4017.

But this will introduce Delay time (1.5 SEC) between the last ring and RESET. But in practice we can neglect it as

not affecting our project aim in any way.

I think this is the most perfect circuit.

Design ------- Quasi length TAKEN 3.3 sec THEN C=100uF R=100K

If have any suggestions pls post…