Hmm, Phillips recommended VDD/GND lines between SCL/SDA on the cable

Qwiic System
1

Doing a little more research (on the recommended 0.1uF decoupling caps actually), ran into this:

http://esd.cs.ucr.edu/webres/i2c20.pdf, Page 42, Section 17.3

The reason for our arrangement of the power lines being between the I2C wires is to stop crosstalk. ie the edges of SDA and SCL coupling together. Placing VDD and GND between SDA and SCL, means that the capacitance on either signal line is equal (for 4 wire cable)

This is the Philips recommendation. The pattern is that set out in section 17.3 of The I2C Bus Specification. (there are recommendations for twisted pair etc)

  • If the length of the bus lines exceeds 10 cm (ribbon cable or on pcbs)
  • This arrangement will have similar capactive loading on SDA and SCL.
  • Where you don’t use pins 5 & 6, it can be better to just use 4 wires. For longer runs, use twist&flat ribbon, or split 5&6 from 1-4
  • avoid bundled cable where the conductors aren’t individually twisted pairs or individually screened
  • VDD and GND are bypassed at both ends of the cable with 100nF capacitors.
1 Like
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Thanks for sharing.

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There are very few situations where i2c lines are longer than 10cm, but if need be that’d make sense to use a cap to decouple 'em

If your design is gonna have long i2c runs it’s probably worth implementing