Here is what I have so far:
Freescale i.MX6SX series single/dual/quad core processor
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx6sx
}
CoreSight Debug Access Port A9…
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
System JTAG Controller
if { [info exists SJC_TAPID] } {
set _SJC_TAPID $SJC_TAPID
} else {
set _SJC_TAPID 0x0891c01d
}
#SDMA
set _SJC_TAPID2 0x2191c01d
#DAP for ARM Cortex A9
set _SJC_TAPID3 0x2191e01d
#ARM Cortex A9
set _SJC_TAPID4 0x1191c01d
#DAP for ARM M4
#???
#ARM Cortex M4
#???
#below needs to change to only use the M4 not A9
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
-expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
GDB target: Cortex-A9, using DAP, configuring only one core
Base addresses of cores:
ARM Cortex -A9 - 0x82150000
core 0 - 0x82152000
set _TARGETNAME $_CHIPNAME.cpu.0
#need to change this for M4…
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x82150000
some TCK cycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.sjc -event post-reset “runtest 100”
proc imx6_dbginit {target} {
General Cortex A8/A9 debug initialisation
cortex_a dbginit
}
Slow speed to be sure it will work
adapter_khz 1000
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
proc imx6_dbginit {target} {
General Cortex A8/A9 debug initialisation
cortex_a dbginit
}
Slow speed to be sure it will work
adapter_khz 1000
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME configure -event reset-assert-post “imx6_dbginit $_TARGETNAME”
$_TARGETNAME configure -event gdb-attach { halt }