IXP425 debug

Development Boards MicroMod
1

I have a board with an IXP425 , and Ethernet controller and a Xilinx chip in to same chain.

After a day and a half of struggling I have now manage to gain access to the processor.

The initial problem was all to do with Xilinx and Intel not wanting to tell me what the chains looked like.

The second major problem was fixed by turning off the jtag_verify_capture_ir flag in the jtag.v file. every now and then all 1’s would come back and the test would fail.

The third problem which I have not solved yet, but have worked around, was that the TRSTn signal will only pulse low for 100ns-200ns. This was not propagating to the system reset as I had specified.

Possible my 2 problems are related, does any body have any experience with similar faults.?

Is there a command to set the length of the TRST pulse?

Dave

2

The following added to the config file may help.

jtag_nsrst_delay 100

jtag_ntrst_delay 100

Regards

Spen

3

I did try changing these values but they are not the reset period but are actually a delay after reset is released before the debugger restarts communications.

Dave

4

Sorry i misread what you were trying todo.

Yes the period that the trst is held is currently fixed - should be approx 5ms.

SRST should be about 50ms.

I am a bit confused as it seems you are using the TRST as a system reset?

Cheers

Spen

5

The board I have has the TRST driving SRTS through a bit of logic

This was added by the designers to solve a problem when the JTAG box they were using to program the Flash had problems, it all long in the past.

I am currently using this to prepare for a new board which is basically the same, but does have the TRST and SRTS wired correctly in my view.

I was seeing the TRST go low for only 200ns not 5ms. Its a bit tricky following the code sequence, but I will go back and see where it is asserted

and see if I can control it.

Dave

PS the new board has a ixp430 which will be another problem.