The problem is when I press 3 or more keys I detect no rising edge on the chassis gpio pin for any of the buttons. One at a time works fine, and so do two keys at a time. So is the circuit wrong or is the problem something else?
I’m lost as to how you are detecting the key presses. The SN74HC595 is an output device. You seem to be sending 1 bit to it and then clocking that bit from one end of your long (composite) shift register to the other. How does the output of that bit interact with a key press to get detected ?
I have to assume that all keys, when pressed, make a connection from their specific SR output back to a single, common input pin. You then decode which key is pressed by knowing which SR bit was “on”, aka the clock count since the bit was loaded into the SR. Pressing and holding a key (or keys) for the entire scan time (the time it takes to clock a bit from one end of the SR to the other) should result in 1 (or more) detections at the input pin, if the circuitry is done correctly.
The only way I can envision this working is if all the SR outputs are pulled up when inactive and the bit being propagated down the SR is a logic 0, and an active low is what is detected as a key press. If this is what you’ve done, I don’t see why multiple simultaneous key presses should be a problem.
OTOH you say …
The problem is when I press 3 or more keys I detect no rising edge on the chassis gpio pin for any of the buttons.
… which doesn’t sound like my concept. So what are you doing ? How is the input pin configured/wired ?
Mee_n_Mac:
I have to assume that all keys, when pressed, make a connection from their specific SR output back to a single, common input pin. You then decode which key is pressed by knowing which SR bit was “on”, aka the clock count since the bit was loaded into the SR. Pressing and holding a key (or keys) for the entire scan time (the time it takes to clock a bit from one end of the SR to the other) should result in 1 (or more) detections at the input pin, if the circuitry is done correctly.
Yes that's right. The only way know which key is pressed is by knowing the clock count which tells me the SR bit. The circuit is setup in the opposite way you describe next. I hope that's the problem after all.
The only way I can envision this working is if all the SR outputs are pulled up when inactive and the bit being propagated down the SR is a logic 0, and an active low is what is detected as a key press. If this is what you’ve done, I don’t see why multiple simultaneous key presses should be a problem.
The common input pin (chassis) is pulled *down*, but each SR output is not pulled down (or up). The bit being propagated through the SR is a logical 1, and the rest of the SR bits are supposed to stay 0. On the first clock cycle the register ought to look like 1000 0000 and 0100 0000 on the second clock.
Ignore this if it makes no sense at all since it may be code related, but when I press each switch individually I get rising edge signals on the input pin (chassis) during the appropriate clock cycle. Is it odd that I’m getting more than one rising edge? When I replace 3 switches with 3 wires I do not get the expected output which would be rising edge signals for each of the three. Instead I get rising edges for the first. When I add a fourth wire I get no rising edges.
After checking the datasheet I see your problem. I thought the HC595 had open collector type outputs … it doesn’t. OC outputs allow to “wire AND” them together w/o causing a problem. Each output would supply either a hard ground w/a logic 0 or a soft pull-up to 5/3.3v w/a logic 1. Thus tying 2 or more outputs together is OK, any logic 0 results in all pins at ground voltage.
But your case is not that. You have active outputs, high and low states. Tying 2 outputs together and trying to have one be a logic 1 (5/3.3v) and the other be a logic 0 (0v) results in a “fight” and there’s no defined winner by spec. Tying more that 2 pins together just makes the situation worse, though apparently 2 logic 0’s win the fight vs a single logic 1 and results in a voltage low enough to be a considered a logic 0 by the input pin. And that’s what your circuit is doing when depressing multiple keys at the same time. Until the bit is shifted into one of the keys, they’re all at logic 0 voltage and that’s semi-OK. But when a logic 1 (5/3.3v) is shifted into any of the depressed keys, you’ve got a single 5/3.3v output tied to multiple 0v outputs. Not good. You need to switch an OC shift register or buffer these outputs.
Mee_n_Mac:
After checking the datasheet I see your problem. I thought the HC595 had open collector type outputs … it doesn’t. . But when a logic 1 (5/3.3v) is shifted into any of the depressed keys, you’ve got a single 5/3.3v output tied to multiple 0v outputs. Not good. You need to switch an OC shift register or buffer these outputs.
Oh. Well if I need a new part anyway, how about switching parts to the SN74HC165 parallel in serial out shift register, since that seems more intuitive anyway? Thanks for the links.
Mee_n_Mac:
What do you mean by buffer these outputs?
To keep what you already have and add to it you could use an open collector output IC, like the 7407 mentioned in the 1'st link, added btw the SR outputs and the keyboard. You then add a pullup resistor on the GPIO input pin but invert your logic, propagate and detect a logic 0.
I suppose you could even just add a Schottky diode btw each SR output and the keyboard. That way a logic 1 output from the SR is blocked, allowing the pullup to make the GPIO input high but an SR logic 0 will still pull down the GPIO input and not fight the other SR outputs. You still invert your logic. You use a Schottky, vs a normal, diode for it’s lower voltage drop thus insuring a logic 0 will be detected.
In both cases above you need to watch the speed of your SR clocking. If it’s too high the keyboard capacitance on the input line may not have sufficient time to recharge to a high state following a key press, with the result that a key press “bleeds” into the next (scanned) key. My guess is that you’re not operating much above 1 MHz anyway so it’s not a big concern. Use a 5k pullup.
Or go with the new SR as an input, which saves you a GPIO pin.
http://files.usbtypewriter.com/animation2.gif