I am in search of a schematic review for a data logger design. My design merges the ATSAMD21 with low power architecture, and is a blend of two OS designs (M0 Adalogger, Bee Data Logger). This design should achieve 10 ma while on (adalogger active draw) // <50 ua while in deep sleep (BDL power architecture).
I am most interested in possible gotchas in achieving low power (back-powering while asleep)…
Features:
-ATSAMD21 MCU
-Real Time Clock (ds3231)
-SD Card Slot
-I2C qwiic port power gated using an LDO with enable pin to MCU
The SAMD21G18 has a quirk where it does not come out of reset correctly if the supply voltage is ramped up slowly. Your design may benefit from a dedicated reset supervisor.
The SD card DATA_OUT may need a pull-up resistor. Re-check the Adafruit design and see if they included one.
You have no battery charging circuit, as far as I can tell. Do you need one?
You have no ESD protection on the USB D+/- lines. Do you need some?
Watch out for leakage current from VBAT through Q1 leaking through D2 (reverse leakage) and R1. It’ll be much higher if you have USB connected but not powered, VBUS will sink current.
The trick to achieving a really low sleep current is to understand all the little parasitic current paths that are powered while the microcontroller is in its low power state. Will there be leakage current sourced from the GPIO pins to (e.g.) the SD card or the RTC or SDA/SCL when those are powered off? You’ll need to figure out how to configure those GPIO pins to give you the lowest sleep current.
@Evan_Lahr : one more thing… It might be worth connecting the DS3231 INT pin to a SAMD GPIO, or even connect it to RESET. That way you could use the RTC alarm to wake or reset the microcontroller. It depends on your application but it might allow you to get the SAMD into an even lower power state - with the oscillator completely stopped?
I would put the DS3231 on the always on power domain, it is designed to be low power. You should connect the INT pin so you can use it to wake the MCU.
There should be a separate bus for I2C devices that have power switched. The pullups for the switched power I2C bus should go to the switched power rail. Many devices do not allow voltage on I/O when power is removed and they may pull the I2C bus down. Some I2C devices may work, but it is better to separate the I2C bus for devices that will be powered down.
You might want to add a FET switch to disconnect the battery voltage divider. That will be a continuous drain, even if only 16.5uA
@PaulZC, @steieio, Many thanks for your recommendations. Attached above is the new version, below is the changelog.
-TPS39600 voltage regulation. LDO voltage regulators were a poor choice: inefficient, and can’t run off vbat < 3.3V (critical for single cell designs), and the ATSAMD21 can run on 1.8V. For these reasons I have gone towards buck/boost regulation, with my peripheral arm also gated by a PFET.
-I have added a reset supervisor similar to the MCP111T in PZC’s iridium beacon
-D2/R1 replaced by the LM22660.
-re parasitic paths:GPIO is limited in this design, so it should only be the pins on the I2C and SPI bus. Power is gated via PFET to all peripherals. I have gotten feedback to add series resistors to SPI lines to limit current yet maintain signal, but I do not fully understand how this impacts rise times and RXTX… Is this worth doing?
-omitted the voltage divider altogether.
-routed all lines required for the JLINK programming into the 2x3 AVR ISP footprint.
Things I did not change: I have left DS3231 on +3.3V // CR1220, as it needs >2.3V. The adafruit SD does not have a DATA_OUT pull up, no change here. No charge circuit, using LiSOCl2. No ESD protection, boards are one-time use.
