I am in search of a schematic review for a data logger design. My design merges the ATSAMD21 with low power architecture, and is a blend of two OS designs (M0 Adalogger, Bee Data Logger). This design should achieve 10 ma while on (adalogger active draw) // <50 ua while in deep sleep (BDL power architecture).
I am most interested in possible gotchas in achieving low power (back-powering while asleep)…
Features:
-ATSAMD21 MCU
-Real Time Clock (ds3231)
-SD Card Slot
-I2C qwiic port power gated using an LDO with enable pin to MCU
The SAMD21G18 has a quirk where it does not come out of reset correctly if the supply voltage is ramped up slowly. Your design may benefit from a dedicated reset supervisor.
The SD card DATA_OUT may need a pull-up resistor. Re-check the Adafruit design and see if they included one.
You have no battery charging circuit, as far as I can tell. Do you need one?
You have no ESD protection on the USB D+/- lines. Do you need some?
Watch out for leakage current from VBAT through Q1 leaking through D2 (reverse leakage) and R1. It’ll be much higher if you have USB connected but not powered, VBUS will sink current.
The trick to achieving a really low sleep current is to understand all the little parasitic current paths that are powered while the microcontroller is in its low power state. Will there be leakage current sourced from the GPIO pins to (e.g.) the SD card or the RTC or SDA/SCL when those are powered off? You’ll need to figure out how to configure those GPIO pins to give you the lowest sleep current.
@Evan_Lahr : one more thing… It might be worth connecting the DS3231 INT pin to a SAMD GPIO, or even connect it to RESET. That way you could use the RTC alarm to wake or reset the microcontroller. It depends on your application but it might allow you to get the SAMD into an even lower power state - with the oscillator completely stopped?
