After studying the datasheets and UM for the LPC11xx series micros, I have some questions about the lower power modes (not limited to Sleep and Deep Sleep).
I have an application where reasonally accurate timing (+/- 5% max) must be kept (with one timer running) with power being as low as possible (sub 10uA with lower being better).
Here’s the problem. In Deep Sleep Mode, the only oscillator available to run a timer is the watchdog oscillator. However, this oscillator has a tolerance of about +/- 40%. Not only that, there appears to be no way to calibrate it. That is, I can’t use the watchdog oscillator to clock one timer while the calibrated 12MHZ RC clocks another timer to calibrate the watchdog oscillator.
The only possible solution that I see right now is to run in active mode at full speed, then when low power is needed, set the System Clock divider to about 240. This will reduce the system clock to 50KHZ. Then I can enter “Normal” Sleep mode with the system clock speed greatly reduced, and shut off the clock to the core. Of course, one timer will be enabled during this time. A timer interrupt will awaken the CPU from sleep. The System Clock divider will be switched back to 1 (12MHZ), then the CPU will evaluate whether or not to awaken, or go back to sleep.
Of course, there are no graphs to show power usage in a mode like this. The datasheet (Fig 10) shows a sleep mode current of approximately 2mA at 12MHZ with all peripheral clocks turned off. This is a little disturbing since it suggests that the 12MHZ IRC draws nearly 2mA all by itself. If this is true, then my method of reducing the System Clock with the divider won’t achieve the desired results since the IRC is still running.
Does anyone have any experience with trying to maintain accurate timing in sleep and deep sleep modes ?
The lack of even remotely precise timing during deep sleep (and accurate timed-wakeup from deep sleep) is for me the biggest drawback of the LPC13xx and LPC11xx microcontrollers. I have repeatedly asked NXP to fix this in a future chip, and I certainly hope they do.
For low-power applications, event-driven programming is needed for efficient and robust implementation. Thus timed-wakeup is a necessity for any sort of delay, timeout, periodic operations, etc., and most applications will need a system time accuracy of much better than +/- 40% – that is completely unacceptable.
My ideal discrete real time clock module (RTC) would be a binary counter with millisecond precision or better. A Y/M/D H:M:S RTC is really useless and clumsy for most uses that I have for accurate time. A precision clock is needed with which arithmetic operations such as addition of an duration and subtraction between two points in time is easy. This means a binary counter based clock. Most devices don’t need to convert to H:M:S format for human presentation, and deferring this step to a more capable device allows proper time zone and daylight savings time adjustments, among other things.
I have been thinking about using an ATmega48P with a 32.768 kHz watch crystal and asynchronous timer/counter 2 as an SPI slave device keeping time and acting as a wakeup timer for the main MCU in an LPC1313 based device. This will provide a fairly simple solution that satisfies all my goals, except that it requires an extra component (the ATmega48P MCU) which means more board space consumed and adds $1.50-$2.00 to a design based around a $3.00 main MCU. Although… this is still cheaper than a Maxim RTC, perhaps? And much more flexible since the no existing RTC matches my goals of 1 ms precision and in a binary counter format.
Thanks for the reply colinb. I was hoping that I had missed something, but apparently not. The LPC11xx has a very attractive feature set and price point, but, the lack of a reasonably accurate clock in deep sleep mode make the processor totally unusable for my application.
Would it have been so hard to allow one of the timers to be clocked from the watchdog oscillator while another timer was clocked with the calibrated RC ? Then a rough calibration of the watchdog osc could be performed to get a reasonably accurate timing source during deep sleep. I have seen micros from ST and TI that allow this type of calibration of the LF oscillator.
External solutions cost extra $$$ and board space. This isn’t something I’m prepared to live with due to a lack of a simple internal switch to select a clock source - especially when there are other solutions. This appears to be an extraordinary oversite on NXP’s part, and will probably be fixed in the future. But, it will be too late for me. However, I will put in my 2 cents worth to NXP in an attempt to get an accurate clock source in deep sleep mode for future products.