It’s a shame, since I think this is going to be the main issue that slows uptake of the new Cortex cores with hobbyists, and I can’t imagine it being resolved in the immediate future (<6 months?). It’s definately above my pay grade to make an SWD debugger and the accompanying software/firmware, much as I"d like to be able to.
Is SWD really necessary to use the LPC11xx?
The user manual indicates in Table 251 that there are JTAG pins TCK (shared with SWCLK), TMS, TDI, TDO, and /TRST.
Also, Section 4.1 (I/O configurations registers IOCON_PIOn) shows that these pins are enabled in this mode after reset.
This would imply that JTAG was available (at the cost of using more pins).
Conflicting this is the statement in Section 4 of Chapter 18 that says “Debugging with the LPC111x uses the Serial Wire Debug mode.”. However, immediately after, it lists the JTAG pins as “various pin functions related to debug.”. Hmm.