It uses CRC and switches from transmit to receive fine.
The important delays as far as I can tell are the 3mS startup, 5uS after setting CS or CE and 500nS setup and hold times on the clock and data. You do have to delay 195uS plus the time to send a packet (Toa) after lowering CE when sending a packet before switching back to receive mode in order to allow the packet to be sent! There is another timing parameter, Td before setting CS or CE when there should be no transitions on CS, CE, CLK or DATA. It’s only 50nS, so it will almost certainly be met on most microcontrollers simply by setting all the lines to zero before setting CS or CE.
You really do only need to send one configuration bit to switch between RX and TX if you meet all the timing parameters.