I noticed that with my 24L01 setup, in order to get the transceiver to transmit or receive, I have to flush the FIFO. It seems as if the receive FIFO never clears itself when you read it (like it says it’s supposed to in the datasheet). I noticed that the Sparkfun code does this as well.
Is this some sort of silicon error that may be resolved in future editions of the chip? If not, it seems like it will significantly eat bandwidth if I have to flush the FIFO after every reception/transmission.