openocd, at91sam9260

Development Boards MicroMod
1

hello,

I’m trying to use an embedded board based on at91sam9260 with openocd.

I use an amontec jtag key.

When i try to start openocd here is what is get:

Info: openocd.c:93 main(): Open On-Chip Debugger (2007-09-05 09:00 CEST)

Error: jtag.c:1301 jtag_examine_chain(): number of discovered devices in JTAG chain (578) doesn’t match configuration (1)

Error: jtag.c:1302 jtag_examine_chain(): check the config file and ensure proper JTAG communication (connections, speed, …)

Error: jtag.c:1440 jtag_init(): trying to validate configured JTAG chain anyway…

Error: jtag.c:1357 jtag_validate_chain(): Error validating JTAG scan chain, IR mismatch, scan returned 0x01

Error: jtag.c:1357 jtag_validate_chain(): Error validating JTAG scan chain, IR mismatch, scan returned 0x01

Error: jtag.c:1357 jtag_validate_chain(): Error validating JTAG scan chain, IR mismatch, scan returned 0x01

Error: jtag.c:1357 jtag_validate_chain(): Error validating JTAG scan chain, IR mismatch, scan returned 0x01

Error: jtag.c:1357 jtag_validate_chain(): Error validating JTAG scan chain, IR mismatch, scan returned 0x01

Error: jtag.c:1357 jtag_validate_chain(): Error validating JTAG scan chain, IR mismatch, scan returned 0x01

Error: jtag.c:1448 jtag_init(): Could not validate JTAG chain, exit

My config is the following:

telnet_port 3333

gdb_port 4444

#interface

interface ft2232

ft2232_device_desc “Amontec JTAGkey A”

ft2232_layout “jtagkey”

ft2232_vid_pid 0x0403 0xcff8

jtag_speed 0

jtag_nsrst_delay 200

jtag_ntrst_delay 0

#use combined on interfaces or targets that can’t set TRST/SRST separately

reset_config trst_and_srst separate

#jtag scan chain

#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)

jtag_device 4 0x1 0xf 0xe

#target configuration

daemon_startup reset

#target

target arm926ejs little reset_halt 0 arm926ejs

run_and_halt_time 0 30

I tried to reduce the jtag clock but i got the same result.

thanks for your help

greg

2

The SAM926x can run from a 32kHz oscillator - in that case you have to reduce the JTAG frequency to about 5kHz (1/6th of the core frequency). Try a jtag_speed setting of about 1200 (6MHz / 1200 = 5kHz). You can increase the JTAG frequency again once the PLL is enabled and selected as the clock source.

Regards,

Dominic

3

dominic,

Unfortunately it doesn’t work even if i set jtag_speed to 1200.

The reset circuitry is identical to the one used in the AT91SAM9260-EK.

When i start openocd and probe nSRST & nTRST signals, i can see that they are active a very short time (about 200ns) !!!

thanks again for your answer

greg