I’m going to need to debug a processor in an FPGA without access to pins for attaching a JTAG dongle to.
Xilinx has an AXI4-Lite to JTAG core available. See:
https://www.xilinx.com/support/document … alinux.pdf
I’d just be using the AXI2JTAG core, and not the “Virtual Cable” software. This is on a Xilinx FPGA, and is using a non-Xilinx supported soft processor core. The axi2JTAG core would be accessed over PCIE as a set of registers.
Has someone done this before?
Is it reasonable to write the configuration file needed? Examples of something similar, documentation?