openOCD + LH75401 - updated- cannot halt target from openocd

Hello,

I recently finished a project using openOCD and ARM-USB-OCD to connect to a STR912 olimex board. I used GNU GCC ARM compiler with the eclipse platform and everything worked so well together, thanks in some part to searching this forum board, I plan to use this setup for a my current project.

The difference from my past project is that my current project requires using the NXP (previously Sharp) LH75401 mico. I believe this should work as I have already successfully compiled a demo program and openOCD documents that it will work with ARM7TDMI-s cores. My demo program was linked to run from external RAM (the LH75401 has no internal ROM).

My question is am I able via the ARM-USB-OCD to simply write my program to external RAM? And what openOCD commands do I use?

I understand that once I cycle power to the target I will lose my program but it seems to be a good starting point to make sure my code is working. Once I have that working I can update my program to reside in external CFI flash and then copy to RAM at startup.

Thanks in advance…

Wayne

Hello,

I updated my firmware so that it is linked to load in flash and run from RAM. So I no longer need a advise on loading to RAM.

I am currently having troubles with openocd halting the target cpu so I can flash the external CFI flash.

I am using openocd-ftd2xx.exe rev.115 and the following configuration:

###
# Filename: openocd_flash_cfi_ftdi.cfg
# Original author: mthomas 5/2007
# Modifications by: wrice 10/2007
###

###
# daemon configuration
###
telnet_port 4000
gdb_port 2000

###
# Interface
###
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG A"
ft2232_layout olimex-jtag
#jtag_speed 1
ft2232_vid_pid 0x15ba 0x0003
jtag_speed 0
jtag_nsrst_delay 500
jtag_ntrst_delay 500

###
# use combined on interfaces or targets that can't set TRST/SRST separately
###
reset_config trst_and_srst
#reset_config trst_and_srst srst_pulls_trst

###
# jtag scan chain (first device being the one closest to TDO)
# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
###
#jtag_device 8 0x1 0x1 0xfe
#jtag_device 4 0x1 0xf 0xe
#jtag_device 5 0x1 0x1 0x1e
jtag_device 4 0x1 0xf 0xe

###
# reset or attach
###
daemon_startup reset

###
# target configuration
# <type> <endianness> <reset mode> <chainpos> <variant>
# target arm7tdmi little run_and_init 0 arm7tdmi
###
target arm7tdmi little run_and_init 0 arm7tdmi
run_and_halt_time 0 30

###
# run target script file
###
#target_script 0 reset openocd_flash_cfi.script

###
# working_area <target#> <address> <size> <'backup'|'nobackup'>
###
#working_area 0 0x60000000 16384 nobackup

###
# flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options...]
# Configure a flash bank at address "base" of "size" bytes with a bus of "bus_width"
# bits formed by chips of "chip_width" bits size using "driver(lpc2000, cfi, 
# at91sam7, str7x or str9x)"
###
#flash bank cfi 0x40000000 0x00200000 2 2 0

Then I telnet the following commands:

arm7_9 dcc_downloads enable
wait_halt
poll

The openocd console outputs this:

Info: openocd.c:82 main(): Open On-Chip Debugger (2006-10-12 18:00 CEST)
Info: server.c:67 add_connection(): accepted ‘telnet’ connection from 0
Error: target.c:1241 handle_wait_halt_command(): timed out while waiting for target halt

I believe my problem is that I cannot halt the processor so I can erase the previous code and flash my new firmware. I have tried to use ‘reset run_and_halt’, ‘reset halt’ and ‘halt’ commands but none stops the target. If I try ‘soft_reset_halt’ my session locks up and I have to manually close down openocd. Also of not is that ‘reset run’ will reset the current firmware , so I know my commands are getting to the target. Any advice on how to halt the processor would very much appreciated.

“wait_halt” itself doesn’t request a target halt - it waits for a halt caused by a previous “halt” or by a breakpoint that’s expected to trigger.

Try “halt” followed by a “wait_halt”.

Usually, when entering commands via telnet, the target will have entered debug state by the time you type in “wait_halt”. The command is primarily meant to be used with scripts.

Regards,

Dominic

Thanks for the reply.

I tried your suggestion but the target still refuses to halt? I also tried running the script file and got the following output:

Open On-Chip Debugger
> script openocd_flash_cfi.script
arm7_9 dcc_downloads enable
dcc downloads are enabled
halt
requesting target halt...
wait_halt
waiting for target halted...
timed out while waiting for target halt
sleep 10
poll
target state: running
flash probe 0
Command probe not found
flash protect 0 0 23 off
Command protect not found
flash erase 0 0 23
Command erase not found
flash write 0 C:\GCCFD\projects\lh75401_flash_demo03\csps\lh754xx\bsps\eoi75401\
examples\bmpimage\eoi75401_bmpimage.bin 0x0
Command write not found
sleep 30
reset run
sleep 10
shutdown

Connection to host lost.

I continued to use the above openocd_flash_cfi_ftdi.cfg file when starting openocd…

Try upgrading to a more recent version of OpenOCD (see www.yagarto.de for windows binaries), and run with “-d -l ” to enable debug output.

Regards,

Dominic

Thanks for the reply…

I downloaded the newest version openOCD-2007_re204 and I get the following log file output:

Debug:   jtag.c:1407 jtag_init(): -
Debug:   ft2232.c:1296 ft2232_init_ftd2xx(): 'ft2232' interface using FTD2XX with 'olimex-jtag' layout (15ba:0003)
Debug:   ft2232.c:1385 ft2232_init_ftd2xx(): current latency timer: 2
Debug:   ft2232.c:1732 olimex_jtag_init(): 80 08 1b
Debug:   ft2232.c:1775 olimex_jtag_init(): 82 09 0f
Debug:   ft2232.c:253 ft2232_speed(): 86 00 00
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: TRST asserted
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: TRST asserted
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   jtag.c:1291 jtag_examine_chain(): JTAG device found: 0x00754061 (Manufacturer: 0x030, Part: 0x0754, Version: 0x0
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: TRST asserted
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   openocd.c:113 main(): jtag init complete
Debug:   embeddedice.c:220 embeddedice_read_reg_w_check(): 4
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: TRST released
Debug:   jtag.c:1197 jtag_reset_callback(): -
Error:   embeddedice.c:181 embeddedice_build_reg_cache(): unknown EmbeddedICE version (comms ctrl: 0x00000000)
Debug:   arm7_9_common.c:707 arm7_9_assert_reset(): target->state: unknown
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: SRST asserted
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: TRST asserted
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: SRST asserted
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   ft2232.c:993 olimex_jtag_reset(): trst: 1, srst: 1, high_output: 0x02, high_direction: 0x0f
Debug:   ft2232.c:993 olimex_jtag_reset(): trst: 0, srst: 1, high_output: 0x03, high_direction: 0x0f
Debug:   arm7_9_common.c:773 arm7_9_deassert_reset(): target->state: reset
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: SRST released
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   ft2232.c:993 olimex_jtag_reset(): trst: 0, srst: 0, high_output: 0x09, high_direction: 0x0f
Debug:   openocd.c:117 main(): target init complete
Debug:   openocd.c:121 main(): flash init complete
Debug:   openocd.c:125 main(): NAND init complete
Debug:   openocd.c:129 main(): pld init complete
Debug:   gdb_server.c:1451 gdb_init(): gdb service for target arm7tdmi at port 2000
Debug:   embeddedice.c:220 embeddedice_read_reg_w_check(): 1
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: TRST released
Debug:   jtag.c:1197 jtag_reset_callback(): -
Error:   arm_jtag.c:38 arm_jtag_set_instr_error_handler(): setting the new JTAG instruction failed, debugging is likely to be broken
Debug:   arm7_9_common.c:929 arm7_9_halt(): target->state: running
Debug:   embeddedice.c:384 embeddedice_write_reg(): 9: 0xffffffff
Debug:   embeddedice.c:384 embeddedice_write_reg(): 11: 0xffffffff
Debug:   embeddedice.c:384 embeddedice_write_reg(): 12: 0x00000100
Debug:   embeddedice.c:384 embeddedice_write_reg(): 13: 0x000000f7
Debug:   embeddedice.c:220 embeddedice_read_reg_w_check(): 4
Debug:   embeddedice.c:220 embeddedice_read_reg_w_check(): 1
<cut> ... </cut>
Debug:   embeddedice.c:220 embeddedice_read_reg_w_check(): 4
Error:   target.c:1354 handle_wait_halt_command(): timed out while waiting for target halt
Debug:   embeddedice.c:220 embeddedice_read_reg_w_check(): 1
Debug:   target.c:1441 handle_reset_command(): -
Debug:   arm7_9_common.c:707 arm7_9_assert_reset(): target->state: running
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: SRST asserted
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   ft2232.c:993 olimex_jtag_reset(): trst: 0, srst: 1, high_output: 0x0b, high_direction: 0x0f
Debug:   arm7_9_common.c:773 arm7_9_deassert_reset(): target->state: reset
Debug:   jtag.c:295 jtag_call_event_callbacks(): jtag event: SRST released
Debug:   jtag.c:1197 jtag_reset_callback(): -
Debug:   ft2232.c:993 olimex_jtag_reset(): trst: 0, srst: 0, high_output: 0x01, high_direction: 0x0f

I don’t know what to make of the first two error lines but the third error seems to be the same issue where I cannot get the target to halt?

regards,

Wayne

Try a slower jtag speed, test with

jtag_speed 10

in the configutation file (higer valuees are slower)

Regards

Magnus