Hi.
Tring to flash at91sam7s256 device got this :
…
Connected to 7r.
Escape character is ‘^]’.
Open On-Chip Debugger
poll
target state: halted
target halted in ARM state due to debug request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x000e6158
flash probe
Command probe not found
…
What I’ve missed ?
TIA
Oops, found missed config lines. Sorry for noise.
Are the NV bit fixes for the Sam7X implemented in this release?
Yes
There is code for NV bits in r78.
This is a special command that gets loded into OpenOcd when
at91sam7 flash is configured. The syntax is:
**at91sam7 gpnvm **num is the flash bank number (usually 0).
This code is experimental, I dont have the 7X part and 7S can only
rewrite nv bits 100 times accordinig to their errata.
Any problem reports, or sucesses, are welcome.
Regards
Magnus
Thanks! Since you seem quite familiar with this, is there a way to reprogram the flash on the SAM7S and SAM7X controllers repeatedly without having to toggle an NV bit each time? That is, set the NV bit to the correct value and not have it get reset during a reflash.
On the 7S the NVM bits only control the brownout detector.
If the SAM-BA boot is not reladed into flash with the boot recovery procedure
then you can simply flash new content over the existing using JTAG/OpenOcd.
If SAM-BA is loaded into flash then the first two protection bits are set and must be cleared before flasing new content over SAM-BA.
If you use JTAG/OpenOcd then SAM-BA is not necessary, you can simply flash new code over the old.
For the 7X, SAM-BA is not loaded into flash but remapped from ROM into the flash adress space when NVM bit 2 is set to 0. (cleared, default after ERASE). So no locking of the corresponing flash sectors is necessary. If you flash using SAM-BA then NVM 2 must be cleared to remap, enable, SAM-BA. Then flash and afterwards set NVM bit 2.
If you use JTAG/OpenOcd then SAM-BA is not necessary so NVM can be left in a set state and you can simply flash new content over the old.
If you try to read the documentation there is confusion about if a cleared NVM bit has the value 0 or 1. It seems the actual bit value is 1, but the staus read is 0 .
Yes I have read the documentation carefully and tested on 7S, but I dont have a 7X.
Magnus