I’ve got two nordics up and running, and I can’t seem to pull more than about 3kbits/second of net throughput from them. I can receive 100 32 byte payloads in about 7.5 seconds.
I’m running 2mbits/sec, enhanced shockburst, 1-byte crc, 5 byte addresses, and a 32 byte payload. I’ve got a bs-2p sending and a PIC 18f8722 receiving. I’ve winnowed the code as far as I can – the only pause in the code is to display the number of every 10th packet (the packet contents are not displayed, just the number of successful receptions). Based on eyeballing the blinking led’s, the xmitter and receiver are not falling out of sync (thereby causing the receiver to miss every nth packet).
I seem to be losing most of my time in shlepping the packet contents into and out of their respective fifos, but I’m only guessing on this. Does anyone have any suggestions for increasing net throughput? I was hoping for much more.
I’m bit-banging on both xmit and rcv, on the bs-2p with the shiftin and shiftout commands. I think the xmit end is as fast as its going to get, and the lack of missed packets would seem to imply that the xmit is the slower of the two. Perhaps I’ll switch the roles of the stamp and pic, just to see what happens.
I’m using a stamp to send because ultimately the xmit will be on a low-end pic, drawing data from eeprom. The current stamp should be faster than that set up.
At some point in the near future, I’m planning on doing a speed analysis for the 24L01’s with my LPC2148 boards. I’ve never really pushed them that hard, and I’ve heard from other places that their transmit times can take quite a while. If you have any time measurements on your actual data throughput, I would definitely be interested to hear that so I have something to compare to when I do mine.
I’m fiddling with them now, but I’ve already reported everything I know so far. With eyeballs and a stopwatch, I get a max of 100 32 byte payloads in 7.5 seconds. That’s a net throughput of of about 3.4 kbits per second. I haven’t checked yet with auto-acknowledge off (since I need it regardless), and I know the packet addresses, headers, crc, etc, add significant overhead, but it still seems slow.
I’m still working under the assumption that the bottle neck is the serial in/out for the payloads. I don’t have the gear to verify this though. If you post your methods and results, I’ll do the same, and maybe we can figure a way to squeeze more speed out of these (otherwise excellent) chips.