I’m running Altium Winter 09, and I have a board that is 4.75"x2.65", and all of the gerber outputs look fine in Camtastic. It’s a four layer board with interior plane layers for ground and Vcc. I setup the DRC to match the specs in the FAQ, and the board passes.
Unfortunately, when I upload, the plane layers look wrong, and the bot computes the area as being nearly twice that (which makes sense looking at the pictures) The plane layers, unlike the top & bottom layers, are offset to the upper left, and look smaller. They definitely don’t look like they do in the output previewer in Altium.
This is more than likely operator error, since this is my first submission. I primarily do schematic entry, but I’m breaking into board design with a new job. This is my first attempt to actually build a board I’ve designed.
Can someone point me to a quick HOWTO on getting Altium to generate acceptable data files?
You could try designating the internal layers as layers instead of planes, and then filling them with a copper pour… That might export properly in a way that Batch PCB can read.
I’m not sure why your planes won’t export properly, though…
I tried Altium, and they suggested centering the output layers on the film, as opposed to the default setting. I tried it, but the plane layers are still screwed up. Other than that, there really aren’t that many buttons to mess with in the exporter.
I’ll try converting to normal signal layers and using pours. It shouldn’t take too long, and I can use the existing plane layers as templates.
If that doesn’t work, I’ll try Altium support again, and perhaps send them the project file.
I’ll find out for sure in a few days. I did a small 4-layer test board for work, and just released the drawings for manufacturing by a “commercial” board vendor. If there is an issue, it should come back soon.
Yep - I redid the plane layers as copper pours, and the bot now sees them correctly. This was mildly annoying, since I had a bunch of split planes, but now, at least, the report is mostly correct. (All of the layers show up correctly)
Now, I just need to figure out how to get the bot to realize that some of the stuff on the silk screen goes beyond the edge of the board - and that is fine. I don’t care if the silk screen gets cut off. (The power plug and RJ-45 jack both extend beyond the board edges)
I may have to create an alternate component with the silk screen altered to fit, but that seems a bit suboptimal. I would assume there is a layer where I specifically draw the board perimeter, but I haven’t figured that out yet.
EDIT - I altered the symbols for components that hang over the edge of the board. I put the full perimeter on mechanical 1, and the partial perimeter on the top silk screen. The component still shows up as a DRC violation in Altium, but the board size is now being correctly computed by the bot.