you can’t debug an LPC2000 uC right out of reset (from 0x0). When the system reset is asserted, the controller keeps the JTAG logic in reset, too. It gets enabled when system reset goes low, but the bootloader disables it again in the first few instructions. After the bootloader verified that CRP isn’t enabled, JTAG access gets reenabled. Until the Debugger has a chance to gain control over the target, hundreds and thousands of instructions already have executed.
The best you can get is using “run_and_halt” or “run_and_init”, specifying a very low run_and_halt time and jtag_n[st]rst_delay settings. You’ll have to experiment with the minimum times (in ms) your board requires.
If doing a debug build is fine for you, place a “b -2” on the reset vector (or at the reset handler), give the target as much time as it needs, attach the debugger, and manually advance past that branch.
Thanks Dominic for your help. However, when I click on the link you gave me I get a message that says the wiki has no text. Is there another link.
I’m not having problems with OpenOCD but am having problems with gdb. I’m used to command line gdb, but if I can get some of the same features using OpenOCD then I want to learn how.