Hey, I have a doubt: From the Datasheet of SAM7S64
SPI - CSR - DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after EACH TRANSFER and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Ok, but, what is EACH TRANSFER??
I set SPI_CSR with 8 bits, so, Do I have a delay between each byte (8bits), ok?
Or do I have a delay between the buffers in PDC? I set in PDC 2 transfers (one in PDC_TPR, and another in TNextPR). Can I have a delay between these 2 buffers without removing the chip select?
I´m asking because I don´t have a scope here… =/
Ok, 33 people saw, and I think the majority didn’t understand what I was asking. I was trying to active the PDC_SPI receive when the first TX buffers reachs 0 and before the second tx buffer starts… but it´s very fast…
I saw today that the delay is between each transfer of 8 bits (or the number of bits set in CSR). This couldn’t solve my problem…
A workaround to my situation was create another buffer to receive trash, with the same length of the first buffer (the command) to be send. Now, I have 4 buffers.
When the counter of lenght of first buffer (Tx and Rx are the same length) reach null, the both (a second TX e the second receive data buffer) are actived “at the same time”. I use “” cause the second RXbuffer will be activated ONE transfer BEFORE the second TXbuffer, so, the first char received is a TRASH. I added the index and finished.