SPI write finishes too soon?

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1

NOTE: I also posted this on the hifive1/sifive forums, but I’m actually using red-v.

I’m using the SPI to talk to a display that uses a DC pin to tell the display if a byte is command or data/param.

I’ve noticed flakeyness so I debugged it further and found out that if I transfer 2 command bytes (together) and then set the DC pin to high, the capture shows that the DC pin is set too soon (see attached image). It’s set in the middle of the 2nd command byte.

I’m using the txmark set to 1 and checking for it after each transfer block is done in a busyloop but it seems it “sets” too soon?

Is there some other way I should check that the SPI writes are completely pushed out of the FIFO?

dc_races_txmark.png
dc_races_txmark.png1417×459 15.5 KB

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Solved: I did a mistake in the loop logic in the combined read/write loop returning before reads had a chance to fully complete (in case the read buffer was actually throw-away/unused)