Hello i’m trying to load U-boot ELF image into two identical Marvell Kirkwood based boards.
I have them connected in JTAG chian like:
JTAG TDI → board1 TDI
board1 TDO → board2 TDI
board2 TDO → JTAG TDO
TCK, TMS, TRST, NRST, GND, VCC signals are common for two boards.
Here is my OpenOCD board configuration file.
–
source [find interface/sheevaplug.cfg]
set CHIPNAME board1
source [find target/feroceon.cfg]
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
-work-area-size 65536 \
-work-area-backup 0
set CHIPNAME board2
source [find target/feroceon.cfg]
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
-work-area-size 65536 \
-work-area-backup 0
arm7_9 dcc_downloads enable
# this assumes the hardware default peripherals location before u-Boot moves it
set _FLASHNAME $_CHIPNAME.flash
nand device $_FLASHNAME orion 0 0xd8000000
proc sheevaplug_init { } {
# We need to assert DBGRQ while holding nSRST down.
# However DBGACK will be set only when nSRST is released.
# Furthermore, the JTAG interface doesn't respond at all when
# the CPU is in the WFI (wait for interrupts) state, so it is
# possible that initial tap examination failed. So let's
# re-examine the target again here when nSRST is asserted which
# should then succeed.
jtag_reset 0 1
board1.cpu arp_examine
board2.cpu arp_examine
halt 0
jtag_reset 0 0
wait_halt
arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 # Dunit Control Low Register
mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register
mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register
mww 0xD0001424 0x0000F17F # Dunit Control High Register
mww 0xD0001428 0x00085520 # Dunit Control High Register
mww 0xD000147c 0x00008552 # Dunit Control High Register
mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
mww 0xD0001508 0x10000000 # CS1n Base Register
mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
mww 0xD0001514 0x00000000 # CS2n Size Register
mww 0xD000151C 0x00000000 # CS3n Size Register
mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register
mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register
mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0010000 0x01111111 # MPP 0 to 7
mww 0xD0010004 0x11113322 # MPP 8 to 15
mww 0xD0010008 0x00001111 # MPP 16 to 23
mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
}
–
Here is OpenOCD log:
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
200 kHz
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
jtag_nsrst_delay: 200
jtag_ntrst_delay: 200
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
jtag_nsrst_delay: 200
jtag_ntrst_delay: 200
dcc downloads are enabled
Warn : use ‘board1.cpu’ as target identifier, not ‘0’
Info : clock speed 200 kHz
Info : JTAG tap: board1.cpu tap/device found: 0x20a023d3 (mfg: 0x1e9, part: 0x0a02, ver: 0x2)
Info : JTAG tap: board2.cpu tap/device found: 0x904023d3 (mfg: 0x1e9, part: 0x0402, ver: 0x9)
Warn : JTAG tap: board2.cpu UNEXPECTED: 0x904023d3 (mfg: 0x1e9, part: 0x0402, ver: 0x9)
Error: JTAG tap: board2.cpu expected 1 of 1: 0x20a023d3 (mfg: 0x1e9, part: 0x0a02, ver: 0x2)
Warn : Unexpected idcode after end of chain: 64 0x0000007f
Warn : Unexpected idcode after end of chain: 128 0x0000007f
Warn : Unexpected idcode after end of chain: 160 0x0000007f
Warn : Unexpected idcode after end of chain: 288 0x8000007f
Warn : Unexpected idcode after end of chain: 384 0x0000007f
Warn : Unexpected idcode after end of chain: 448 0x0000007f
Warn : Unexpected idcode after end of chain: 480 0x0000007f
Warn : Unexpected idcode after end of chain: 608 0x0000007f
Error: double-check your JTAG setup (interface, speed, missing TAPs, …)
Info : JTAG tap: board1.cpu tap/device found: 0x20a023d3 (mfg: 0x1e9, part: 0x0a02, ver: 0x2)
Info : JTAG tap: board2.cpu tap/device found: 0x20a023d3 (mfg: 0x1e9, part: 0x0a02, ver: 0x2)
Info : Embedded ICE version 0
Info : board1.cpu: hardware has 1 breakpoint/watchpoint unit
Info : Embedded ICE version 0
Info : board2.cpu: hardware has 1 breakpoint/watchpoint unit
Trying ::1…
Trying 127.0.0.1…
Connected to localhost.
Escape character is ‘^]’.
Open On-Chip Debugger
reset
JTAG tap: board1.cpu tap/device found: 0x20a023d3 (mfg: 0x1e9, part: 0x0a02, ver: 0x2)
JTAG tap: board2.cpu tap/device found: 0x20a023d3 (mfg: 0x1e9, part: 0x0a02, ver: 0x2)
targets
TargetName Type Endian TapName State
0* board1.cpu feroceon little board1.cpu running
1 board2.cpu feroceon little board2.cpu running
invalid mode value encountered 0
cpsr contains invalid mode value - communication failure
ThumbEE – incomplete support
target state: halted
target halted in ThumbEE state due to debug-request, current mode: System
cpsr: 0xffffffff pc: 0xfffffff9
MMU: enabled, D-Cache: enabled, I-Cache: enabled
invalid mode value encountered 4
cpsr contains invalid mode value - communication failure
sheevaplug_init
Halt timed out, wake up GDB.
timed out while waiting for target halted
Command handler execution failed
in procedure ‘sheevaplug_init’ called at file “command.c”, line 650
in procedure ‘wait_halt’ called at file “/usr/share/openocd/scripts/board/two_boards.cfg”, line 43
called at file “command.c”, line 361
timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 0
timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 0
timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 0
timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 0
timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 0
timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 0
target state: halted
target halted in Thumb state due to debug-request, current mode: FIQ
cpsr: 0x00002a31 pc: 0xffffffea
MMU: enabled, D-Cache: enabled, I-Cache: enabled
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
So finally I can not invoke load_image /srv/tftp/u-boot and resume 0x00600000
The question is what am I doing wrong and has anybody tried to connect two kirkwood boards in JTAG chain.