I have made a delay line made up of a series of 74AC14 logic gates, the stimulus is a 80MHZ clock, the question is can you go on delaying the signal for ever with unlimited 74AC14 logic gates and is there a finite point when signal integrity will be a problem.
The transition delay for each logic gate is about 3nS, so for a 80Mhz clock signal with six gates I delay it by 18nS
I looked at the TI datasheet for this part. It’s a common part so there many potential suppliers. Make sure you check the datasheet from the supplier for the parts you have.
On the datasheet I note two things that might impact a long string of 74AC14 gates strung together. The first is that the worst case gate delay is much longer than the period of the 80MHz clock. This means that in gates working at that worst case the input changes well before the whole gate circuit has switched states. In that situation it is possible that the output will not switch completely. It could happen that there is not enough of a swing to trigger the next gate. Note that this is not the effect of a string of gates. It could happen in a single gate, but having more gates in your circuit increases the odds of it happening. Also, gate delay changes with temperature so just because it works at room temperature does not mean it will work at higher or lower temperatures.
The second item to note is that the output delays are not perfectly symmetrical between hi-to-lo and lo-to-hi. That means that a 50% duty cycle clock going in is not exactly 50% coming out. You can hope the because it is inverted the next gate will shift it back to 50% again, but I’m not certain that it will. It may be that with a sufficiently long chain of gates the duty cycle continues to shift in one direction or the other eventually hitting 0% or 100% which would of course be the end of the clock. I have no estimate of how many gates that would take.
Somehow I dropped a decimal in thinking about the period compared to the gate delay. In actuality the period of 80MHz (12.5nS) is just about the same as the worst delay through the 74AC14. However my argument still holds as the clock “pulse” at 50% duty cycle is still substantially shorter than the gate delay. As long as the gate delay stays in the “typical” range everything is fine, but if temperature shifts or you get a batch that is at the end of the spec the circuit could stop working.