Wishbone Protocol

Archive SparkFun Site Questions/Comments
1

I have started to work with FPGAs recently, and have been running into a few problems

  1. Multiple modules using a single peripheral gets very confusing with awkard combinational logic

  2. Interacting with multiple resources from a single processor, or interface is a little bit of a pain itself

  3. Trying to figure out how to incorporate other peoples code into my own is itself very frustrating.

I have been working on the older nokia camera which busonerd had cracked a while ago to work with my http://www.charmedlabs.com XPORT FPGA, and finally I got it working to display things on my Nintendo DS (Another post) but a coworker had introduced me to wishbone

wishbone is a protocol for HDL, it can be written in VHDL or verilog, and can be used to

  1. Share a single peripheral

  2. Interact with multiple resource from a single processor (soft or hard)

  3. Since its a protocol then the barriers between sharing source is broken down a little bit more

I dont see too many FPGA projects on this site, but Im sure that all the intelligent people I learn from here will be getting to them in due time, and I would like to point these peoples attention to http://www.opencores.org The site is not the best, but it does have some fairly good examples.

I am working on a wishbone version for the camera right now, that I can hopefully post on a soon to come website. I hope that this protocol will become popular, making the task of designing verilog interfaces for LCDs, Cameras, and other exciting things not a redundant process.

Perhaps in the future we can get a scripting language or gui interface to wirite our verilog, or VHDL code for interconnects, and arbitrators.

Cospan