So as a project to get my hands wet with FPGA goodness, I wanted to write a logger that reads data going to and from this chip:
http://datasheet.octopart.com/MX25L2563 … 291205.pdf
The FPGA is a 3rd wheel. It’s neither a master nor a slave.
Here is my code so far:
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-- Company:
-- Engineer:
--
-- Create Date: 21:43:47 12/31/2013
-- Design Name:
-- Module Name: SPILogger - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SPILogger is
Port ( SPI_CLK : in STD_LOGIC;
SPI_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Enable : in STD_LOGIC;
UART_TXD : out STD_LOGIC;
CLK : in STD_LOGIC;
Chip_Select : in STD_LOGIC);
end SPILogger;
architecture Behavioral of SPILogger is
COMPONENT FIFOModule
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
signal SPI_WRITE_BITS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal SPI_READ_BITS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal WriteCount : STD_LOGIC := '0';
signal FIFO_RESET : STD_LOGIC := '0';
signal FIFO_WRITE_ENABLE : STD_LOGIC := '0';
signal FIFO_READ_ENABLE : STD_LOGIC := '0';
signal FIFO_FULL : std_logic;
signal FIFO_EMPTY : std_logic;
begin
myFIFO : FIFOModule
PORT MAP (
rst => FIFO_RESET,
wr_clk => SPI_CLK,
rd_clk => CLK,
din => SPI_WRITE_BITS,
wr_en => FIFO_WRITE_ENABLE,
rd_en => FIFO_READ_ENABLE,
dout => SPI_READ_BITS,
full => FIFO_FULL,
empty => FIFO_EMPTY
);
Logger: process (SPI_CLK)
begin
if (rising_edge(SPI_CLK) and Chip_Select = '0') then
FIFO_WRITE_ENABLE <= '0';
if (WriteCount = '0') then
SPI_WRITE_BITS(7) <= SPI_IN(3);
SPI_WRITE_BITS(6) <= SPI_IN(2);
SPI_WRITE_BITS(5) <= SPI_IN(1);
SPI_WRITE_BITS(4) <= SPI_IN(0);
WriteCount <= '1';
else
--Write to the FIFO, set count back to 0
SPI_WRITE_BITS(3) <= SPI_IN(3);
SPI_WRITE_BITS(2) <= SPI_IN(2);
SPI_WRITE_BITS(1) <= SPI_IN(1);
SPI_WRITE_BITS(0) <= SPI_IN(0);
FIFO_WRITE_ENABLE <= '1';
WriteCount <= '0';
end if;
end if;
end process;
Transmitter : process (CLK)
begin
--if (rising_edge(CLK) and FIFO_EMPTY = '0')
-- Grab Bits from FIFO and send to UART.
--end if;
end process;
end Behavioral;
My main question is about my writing to the FIFO. On the rising edge, I set the remaining 4 data pins, and then enable write enable. Is this the best way to do this? What happens if write enable reaches the FIFO before the data, it will just write junk to the FIFO?
My plan is to setup some kind of finite statemachine in the logging process, because data is sent back on falling edge. So I need to know what state the flash module is in to correctly log everything.