How is A/D conversion usually handled when using FPGAs?
It seems that with the potential for unclocked signals passing through the gates, high accuracy or high frequency signals could be compared or mixed, but with the thought I have in mind, the issue is getting analog signals “into” the array quickly without sample delays.
Generally, most FPGA companies provide an IP that you use to get this data and configure it the way you want. From here, the data is either stored, or sent over AXI to another IP.
Xilinx provides instantiation templates of the ADC which you can modify to handle it the way you want. Since I usually work on 7-series parts, they have an IP specifically designed for this (XADC).
How do FPGAs handle ADC? It all depends on if you are doing ADC on the FPGA, or if you’re integrating a 3rd party chip. Doing it on an FPGA requires that you don’t exceed certain voltage requirements, and using a 3rd party chip requires that it can properly interface either digitally or analog.
If you do the ADC on the FPGA, then it utilizes the clocking structure you provide to do the comparison (similar to the way an MCU does it).
Xilinx has written some white papers on doing this, that you might want to check out that should provide you some more detailed info.
TrollHammer
As sgrace mentioned the 7 series of Xilinx parts has an A/D feature that you can implement using the XADC core. All you need outside the device is the recommended filter of two resistors and one cap per XADC input.
XIlinx has some appnotes about this but you should read app note UG480 first as this covers the XADC. The other option is an external A/D.
I have some XADC implementations under my belt so if you get stuck, shoot me a message and I will help how I can.
Purple Squirrel