First, greetings to all here, I have just signed in. The reason is a problem what I have with the wiggler interface on an LPC board. I know, there are already some posts related to this but no final solution yet.
This is mainly addressed to Dominic but I post it here since this is surely from interrest to some others as well.
The board I use is an EmbeddedArtists LPC2132 board using a 10MHz crystal. The RTCK pin is pulled down. For development I use the latest YAGARTO tool set and openOCD r128. The wiggler is based on the schematics in the openOCD documentation. The following configuration is used:
#daemon configuration
telnet_port 4444
gdb_port 3333
#interface
interface parport
parport_port 0x378
parport_cable wiggler
jtag_speed 0
#use combined on interfaces or targets that can’t set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe
jtag_nsrst_delay 500
jtag_ntrst_delay 500
#target configuration
daemon_startup reset
#target arm7tdmi
target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
run_and_halt_time 0 30
working_area 0 0x40000000 0x4000 nobackup
#flash configuration
flash bank lpc2000 0x0 0x10000 0 0 lpc2000_v2 0 10000 calc_checksum
When I try to connect to the board, I get the following output:
c:\Programme\YAGARTO\openocd-2007re128\bin>openocd-pp -f .\configs\lpc2132_wiggler.cfg -d 3
Info: openocd.c:84 main(): Open On-Chip Debugger (2006-01-26 13:30 CET)
Debug: jtag.c:1307 jtag_init():
Debug: parport.c:377 parport_init(): requesting privileges for parallel port 0 x378…
Debug: parport.c:387 parport_init(): …privileges granted
Debug: parport.c:212 parport_reset(): trst: 0, srst: 0
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 1
Debug: jtag.c:1106 jtag_reset_callback():
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 1
Debug: jtag.c:1106 jtag_reset_callback():
Error: jtag.c:1159 jtag_examine_chain(): JTAG communication failure, check connection, JTAG interface, target power etc.
c:\Programme\YAGARTO\openocd-2007re128\bin>
I am quite sure, that the wiggler is working. I checked all signals with the oscilloscope, they have about 0 / 4.5 volts on the pc side and 0 / 3.3 volts on ARM side. Then I connected a logic analyser to the ARM side of the wiggler on all 6 signals and found the following which is confusing me:
When idle, nTRST, TDI, TCK and TDO shows a low level, nSRST and TMS show a high level.
According to my configuration, I expect at first, that nTRST and nSRTS will both go low for about 500 ms and after that communication will start. But in true, nSRST keeps high all the time and nTRST is low, goes high for about 100 µs, goes low again and remains then low all the time.
While nTRST is still low, TMS is going high and 7 TCK pulses are seen. After about hundred µs another 3 TCK’s are seen. Next, the TAP state “capture DR” is selected and so on.
But this all while nTRST is low. Can this work?
If I manually disconnect nTRST, I get the following output:
c:\Programme\YAGARTO\openocd-2007re128\bin>openocd-pp -f .\configs\lpc2132_wiggler.cfg -d 3
Info: openocd.c:84 main(): Open On-Chip Debugger (2006-01-26 13:30 CET)
Debug: jtag.c:1307 jtag_init():
Debug: parport.c:377 parport_init(): requesting privileges for parallel port 0x378…
Debug: parport.c:387 parport_init(): …privileges granted
Debug: parport.c:212 parport_reset(): trst: 0, srst: 0
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 1
Debug: jtag.c:1106 jtag_reset_callback():
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 1
Debug: jtag.c:1106 jtag_reset_callback():
Debug: jtag.c:1192 jtag_examine_chain(): JTAG device found: 0x4f1f0f0f (Manufacturer: 0x787, Part: 0xf1f0, Version: 0x4
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 1
Debug: jtag.c:1106 jtag_reset_callback():
Debug: openocd.c:102 main(): jtag init complete
Debug: embeddedice.c:203 embeddedice_read_reg_w_check(): 4
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 3
Debug: jtag.c:1106 jtag_reset_callback():
Debug: arm7_9_common.c:656 arm7_9_assert_reset(): target->state: unknown
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 0
Debug: jtag.c:1106 jtag_reset_callback():
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 1
Debug: jtag.c:1106 jtag_reset_callback():
Warning: arm7_9_common.c:683 arm7_9_assert_reset(): srst resets test logic, too
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 0
Debug: jtag.c:1106 jtag_reset_callback():
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 1
Debug: jtag.c:1106 jtag_reset_callback():
Debug: parport.c:212 parport_reset(): trst: 1, srst: 1
Debug: parport.c:212 parport_reset(): trst: 1, srst: 1
Debug: arm7_9_common.c:722 arm7_9_deassert_reset(): target->state: reset
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 2
Debug: jtag.c:1106 jtag_reset_callback():
Debug: parport.c:212 parport_reset(): trst: 0, srst: 0
Debug: openocd.c:106 main(): target init complete
Debug: openocd.c:110 main(): flash init complete
Debug: openocd.c:114 main(): pld init complete
Debug: gdb_server.c:1347 gdb_init(): gdb service for target arm7tdmi at port 3333
Debug: embeddedice.c:203 embeddedice_read_reg_w_check(): 1
Debug: jtag.c:258 jtag_call_event_callbacks(): jtag event: 3
Debug: jtag.c:1106 jtag_reset_callback():
Warning: jtag.c:1048 jtag_read_buffer(): value captured during scan didn’t passthe requested check: captured: 0x04 check_value: 0x01 check_mask: 0x0f
Error: arm7_9_common.c:610 arm7_9_poll(): JTAG queue failed while reading EmbeddedICE status register
c:\Programme\YAGARTO\openocd-2007re128\bin>
So my questions are:
Is the implementation of the reset handling somehow broken in the r128?
What other reasons can this behaviour have?
If neccessary, I can provide some screenshots of the logic analyser output . Thanks a lot in advance and have a nice day (evening)!
Bernhard