In the errata sheet for the LPC2138 (Rev E), it says the following:
Port pin P0.31 must not be driven low during reset. If low on reset the device behaviour is undetermined.
P0.31 is the TRST signal that connects to the JTAG pod.
I’m using the Olimex ARM-USB-OCD with OpenOCD. Has anyone experienced any problems using this with Rev E of the processor?
We had a board with the Rev B processor and everything seemed to work fine including debugging with the ARM-USB-OCD and OpenOCD.
I run the script for OpenOCD and when I monitor the reset and trst lines, I see trst being held low during reset. Is this expected? We just spun a new board with Rev E. I don’t get any errors when I run the OpenOCD script and start debugging, however I sometimes see weird register settings when I break in the code. Now, I’m sure there are probably other problems with the board that may or may not be related to this so I’m trying to narrow it down a bit.
Is there anything I can change in the OpenOCD script that will assert the reset, then deassert it, then assert trst and deassert it? From what I understood from reading the errata was that reset and trst can’t be asserted at the same time. I tried playing around with the jtag_nsrst_delay/jtag_ntrst_delay and jtag_nsrst_assert_width/jtag_ntrst_assert_width, however I’m still ending up with both of them asserting at the same time.
Thanks.
Hardeep