Pictures about Reset on LPC2138 vs stm32

SimonQian · June 21, 2008, 4:52pm

Does the reset problem of LPC2138 solved?

I captured picture about reset singal when operating LPC2138 and STM32, hope it will be helpful.

STM32(It’s OK):

http://www.SimonQian.com/image/temp/jtag_stm32.jpg

LPC2138(It’s OK before Reset):

http://www.SimonQian.com/image/temp/jtag_2148.jpg

The reset singals are different becasue of the settings.

For STM32: reset_config trst_and_srst

For LPC2138: reset_config trst_and_srst srst_pulls_trst

Another question:

Is it OK if I modify tap_move to (every element is 8bits):

8 OLINK_tap_move[6][6] =
{
/*	  TLR   RTI   SD    PD    SI    PI             */
	{0xff, 0x00, 0x2f, 0x0a, 0x37, 0x16},	/* TLR */
	{0xff, 0x00, 0x4a, 0x05, 0x56, 0x0b},	/* RTI */
	{0xff, 0x31, 0x00, 0x01, 0x0f, 0x2f},	/* SD  */
	{0xff, 0x30, 0x40, 0x17, 0x3c, 0x2f},	/* PD  */
	{0xff, 0x31, 0x07, 0x17, 0x00, 0x01},	/* SI  */
	{0xff, 0x30, 0x38, 0x17, 0x40, 0x2f}	/* PI  */
};

My JTAG tool use 2 spi interface to emulate a JTAG interface, so the operation can only be in 8 bits.

SimonQian · June 22, 2008, 6:05pm

I have found one error, not enough delay after reset will make it misfunction.

SimonQian · June 22, 2008, 6:11pm

Another clue:

If I configure reset_config to “trst_and_srst srst_pulls_trst”:

Debug:   100 1328 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   101 1328 target.c:411 target_process_reset(): Waiting for halted stated as approperiate
Debug:   102 1328 arm7_9_common.c:960 arm7_9_halt(): target->state: running
Debug:   103 1328 embeddedice.c:397 embeddedice_write_reg(): 9: 0xffffffff
Debug:   104 1328 embeddedice.c:397 embeddedice_write_reg(): 11: 0xffffffff
Debug:   105 1328 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000100
Debug:   106 1328 embeddedice.c:397 embeddedice_write_reg(): 13: 0x000000f7
Debug:   107 1328 target.c:425 target_process_reset(): Polling target
Debug:   109 1843 target.c:425 target_process_reset(): Polling target
Debug:   111 2343 target.c:425 target_process_reset(): Polling target
Debug:   113 2843 target.c:425 target_process_reset(): Polling target
Debug:   115 3359 target.c:425 target_process_reset(): Polling target
Debug:   117 3859 target.c:425 target_process_reset(): Polling target
Debug:   119 4359 target.c:425 target_process_reset(): Polling target
Debug:   121 4875 target.c:425 target_process_reset(): Polling target
Debug:   123 5375 target.c:425 target_process_reset(): Polling target
Debug:   125 5875 target.c:425 target_process_reset(): Polling target
Debug:   127 6390 target.c:425 target_process_reset(): Polling target
User:    128 6390 target.c:436 target_process_reset(): Timed out waiting for halt after reset

If I configure reset_config to “srst_only srst_pulls_trst”:

Debug:   93 1328 target.c:411 target_process_reset(): Waiting for halted stated as approperiate
Debug:   94 1328 arm7_9_common.c:960 arm7_9_halt(): target->state: running
Debug:   95 1328 embeddedice.c:397 embeddedice_write_reg(): 9: 0xffffffff
Debug:   96 1328 embeddedice.c:397 embeddedice_write_reg(): 11: 0xffffffff
Debug:   97 1328 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000100
Debug:   98 1328 embeddedice.c:397 embeddedice_write_reg(): 13: 0x000000f7
Debug:   99 1328 target.c:425 target_process_reset(): Polling target
Debug:   100 1344 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   101 1344 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   102 1344 arm7_9_common.c:1074 arm7_9_debug_entry(): target entered debug from ARM state
Debug:   103 1360 arm7_9_common.c:1106 arm7_9_debug_entry(): target entered debug state in System mode
Debug:   104 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r0: 0xffffffff
Debug:   105 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r1: 0xffffffff
Debug:   106 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r2: 0xffffffff
Debug:   107 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r3: 0xffffffff
Debug:   108 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r4: 0xffffffff
Debug:   109 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r5: 0xffffffff
Debug:   110 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r6: 0xffffffff
Debug:   111 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r7: 0xffffffff
Debug:   112 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r8: 0xffffffff
Debug:   113 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r9: 0xffffffff
Debug:   114 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r10: 0xffffffff
Debug:   115 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r11: 0xffffffff
Debug:   116 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r12: 0xffffffff
Debug:   117 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r13: 0xffffffff
Debug:   118 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r14: 0xffffffff
Debug:   119 1360 arm7_9_common.c:1137 arm7_9_debug_entry(): r15: 0xffffffe7
Debug:   120 1360 arm7_9_common.c:1143 arm7_9_debug_entry(): entered debug state at PC 0xffffffe7
Debug:   121 1360 target.c:724 target_call_event_callbacks(): target event 0

SimonQian · June 24, 2008, 7:48am

A bug in code:

arm7tdmi_clock_data_in_endianness function in arm7tdmi.c, if DEBUG_INSTRUCTION_EXECUTION is set, LOG_DEBUG(“in: 0x%8.8x”, *in); will raise an error, I changed it to LOG_DEBUG(“in: 0x%8.8x”, (u32)in);

My gcc version is 3.4.5

ntfreak · June 24, 2008, 9:20am

Thanks i will commit changes to svn.

The best place for this sort of post is the openocd dev list:

https://lists.berlios.de/mailman/listin … evelopment

Cheers

Spen

SimonQian · June 25, 2008, 7:08pm

Found a bug in my driver, and now(SVN 727):

Debug:   106 1781 target.c:423 target_process_reset(): Waiting for halted stated as approperiate
Debug:   107 1781 arm7_9_common.c:965 arm7_9_halt(): target->state: running
Debug:   108 1781 embeddedice.c:397 embeddedice_write_reg(): 9: 0xffffffff
Debug:   109 1781 embeddedice.c:397 embeddedice_write_reg(): 11: 0xffffffff
Debug:   110 1781 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000100
Debug:   111 1781 embeddedice.c:397 embeddedice_write_reg(): 13: 0x000000f7
Debug:   112 1781 target.c:437 target_process_reset(): Polling target
Debug:   113 1797 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   114 1797 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   115 1797 arm7_9_common.c:1079 arm7_9_debug_entry(): target entered debug from ARM state
Error:   116 1812 armv4_5.h:114 armv4_5_mode_to_number(): invalid mode value encountered
Error:   117 1812 arm7_9_common.c:1107 arm7_9_debug_entry(): cpsr contains invalid mode value - communication failure
Warning: 119 2312 arm7_9_common.c:700 arm7_9_poll(): DBGACK set while target was in unknown state. Reset or initialize target.
Debug:   120 2312 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   121 2312 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   122 2312 arm7_9_common.c:1079 arm7_9_debug_entry(): target entered debug from ARM state
Error:   123 2328 armv4_5.h:114 armv4_5_mode_to_number(): invalid mode value encountered
Error:   124 2328 arm7_9_common.c:1107 arm7_9_debug_entry(): cpsr contains invalid mode value - communication failure
Debug:   125 2328 target.c:437 target_process_reset(): Polling target
Warning: 126 2328 arm7_9_common.c:700 arm7_9_poll(): DBGACK set while target was in unknown state. Reset or initialize target.
Debug:   127 2328 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   128 2328 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   129 2328 arm7_9_common.c:1079 arm7_9_debug_entry(): target entered debug from ARM state
Error:   130 2344 armv4_5.h:114 armv4_5_mode_to_number(): invalid mode value encountered
Error:   131 2344 arm7_9_common.c:1107 arm7_9_debug_entry(): cpsr contains invalid mode value - communication failure
Warning: 133 2844 arm7_9_common.c:700 arm7_9_poll(): DBGACK set while target was in unknown state. Reset or initialize target.
Debug:   134 2844 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   135 2844 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   136 2859 arm7_9_common.c:1079 arm7_9_debug_entry(): target entered debug from ARM state
Error:   137 2859 armv4_5.h:114 armv4_5_mode_to_number(): invalid mode value encountered
Error:   138 2859 arm7_9_common.c:1107 arm7_9_debug_entry(): cpsr contains invalid mode value - communication failure
Debug:   139 2859 target.c:437 target_process_reset(): Polling target
Warning: 140 2875 arm7_9_common.c:700 arm7_9_poll(): DBGACK set while target was in unknown state. Reset or initialize target.
Debug:   141 2875 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   142 2875 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   143 2875 arm7_9_common.c:1079 arm7_9_debug_entry(): target entered debug from ARM state
Error:   144 2891 armv4_5.h:114 armv4_5_mode_to_number(): invalid mode value encountered
Error:   145 2891 arm7_9_common.c:1107 arm7_9_debug_entry(): cpsr contains invalid mode value - communication failure
Warning: 147 3391 arm7_9_common.c:700 arm7_9_poll(): DBGACK set while target was in unknown state. Reset or initialize target.
Debug:   148 3391 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   149 3391 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   150 3391 arm7_9_common.c:1079 arm7_9_debug_entry(): target entered debug from ARM state
Error:   151 3406 armv4_5.h:114 armv4_5_mode_to_number(): invalid mode value encountered
Error:   152 3406 arm7_9_common.c:1107 arm7_9_debug_entry(): cpsr contains invalid mode value - communication failure
Debug:   153 3406 target.c:437 target_process_reset(): Polling target
Warning: 154 3406 arm7_9_common.c:700 arm7_9_poll(): DBGACK set while target was in unknown state. Reset or initialize target.
Debug:   155 3406 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   156 3406 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   157 3406 arm7_9_common.c:1079 arm7_9_debug_entry(): target entered debug from ARM state
Error:   158 3422 armv4_5.h:114 armv4_5_mode_to_number(): invalid mode value encountered
Error:   159 3422 arm7_9_common.c:1107 arm7_9_debug_entry(): cpsr contains invalid mode value - communication failure
Warning: 161 3937 arm7_9_common.c:700 arm7_9_poll(): DBGACK set while target was in unknown state. Reset or initialize target.
Debug:   162 3937 embeddedice.c:397 embeddedice_write_reg(): 0: 0x00000005
Debug:   163 3937 embeddedice.c:397 embeddedice_write_reg(): 12: 0x00000000
Debug:   164 3937 arm7_9_common.c:1079 arm7_9_debug_entry(): target entered debug from ARM state
Debug:   165 3953 arm7_9_common.c:1111 arm7_9_debug_entry(): target entered debug state in System mode
Debug:   166 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r0: 0x00000021
Debug:   167 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r1: 0xe0028000
Debug:   168 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r2: 0x2811ffde
Debug:   169 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r3: 0x00800000
Debug:   170 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r4: 0x00000000
Debug:   171 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r5: 0x40001f88
Debug:   172 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r6: 0x00000458
Debug:   173 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r7: 0x8000005f
Debug:   174 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r8: 0x00000000
Debug:   175 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r9: 0x00000000
Debug:   176 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r10: 0x00040000
Debug:   177 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r11: 0x00000000
Debug:   178 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r12: 0x03fc0000
Debug:   179 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r13: 0xffff6812
Debug:   180 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r14: 0x00000544
Debug:   181 3953 arm7_9_common.c:1142 arm7_9_debug_entry(): r15: 0xffffffe8
Debug:   182 3953 arm7_9_common.c:1148 arm7_9_debug_entry(): entered debug state at PC 0xffffffe8
Debug:   183 3953 target.c:736 target_call_event_callbacks(): target event 0
Debug:   184 3953 target.c:437 target_process_reset(): Polling target

It seems that the EmbededICE-RT chain runs OK, but Debug chain fails.

I’ll try to find out why.

If I use scripts in configuration, the R0 - R15 will be different.

I think I found the problem.

SimonQian · June 26, 2008, 3:47am

It’s OK now.

Topic		Replies	Views
Confusion about reset_config MicroMod arm-lpc	7	3610	January 19, 2007
LPC2138 (Rev E) and OpenOCD MicroMod arm-lpc	0	500	October 1, 2010
JTAG MicroMod arm-lpc	1	2386	December 15, 2005
TRST usage with LPC21xx MicroMod arm-lpc	3	2403	February 8, 2007
lpc2138 and openocd problem MicroMod arm-lpc	6	3267	November 4, 2009

Pictures about Reset on LPC2138 vs stm32

Related topics