arm assembler optimization...

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1

a long time ago, I read that risc processor where unable to use successfully the same register

for example: hypothetical processor

ldr r0,=some_label

nop

nop

ldr r0,[r0]

nop

nop

some other instructions

I heard that bad compiler inserted nop to wait until the register was ready…

and good compiler were interleaving the register so that 2 instruction would never be use with the same

register in a row…

what happens with arm processor in such a sequence ?

ldr r0,=some_label

ldr r0,[r0]

some other instructions

  • is it necessary avoid the use of the same register in a series of instructions ?

  • is the arm adding wait states to be sure that the register is available ?

  • what really does DMB DSB ?

  • any references on the web ?

thanks

2

Take a look at the ARM technical reference manual for the specific CPU you are using. While they are all called ARM there are actually many different versions, and some of the earliest versions had the type of limitations you describe.

The architecture is pipe-lined meaning more than 1 instruction is executed concurrently. The pipelines are now complex enough to either take copies of the register, or to freeze conflicting pipes until the conflict is resolved. Compilers no longer insert NOPs, not sure it ever did after the earliest parts.

In some of the bigger parts access to peripherals and or memory can be queued up and actually executed out of order without setting various conditions. So it gets real interesting. Some peripherals are on faster busses than others so without forcing order things may happen out of order.

All in the name of getting faster performance. I’m sure glad I’m not designing CPUs anymore.

3

It’s very interesting, I checked several arm datasheet.

it seems that the strongarm had the problem of delay

(I found table of instruction timing for this processor with the timing + delay before reuse)

Nothing found for the cortex M3 and my programs are working so I think

it’s ok if I don’t take special care about register accesses.

thanks