Does LDR into PC interact with the pipeline?

Hi,

I’m just beginning to code for the LPC-2378, and trying to understand how basic things work. I’ve seen start-up code that sets up the vector table as follows:

(at 0x00000000)

Reset: LDR PC, Reset_Addr

Reset_Addr: DCD Reset_Hdlr

My understand is they’re using LDR instead of B because this lets you jump to anywhere in the 32-bit memory space (i.e. the target address doesn’t get crammed into the instruction word using fewer bits).

But the PC is always two words ahead of the instruction being executed. If you change the value of the PC, won’t you still execute the very next instruction before “jumping” to the new address?

I have been studying documentation for more than a year on-and-off, and don’t remember coming across this.

After any modification to the PC, the CPU stops executing instructions for however many cycles it takes to reload the pipeline starting at the new PC value.

There are some architectures that do execute the instruction immediately following any change the the PC, on the grounds that it’s already been fetched, and would take no time to execute that wouldn’t otherwise be wasted (and you can always put a no-op there if you really don’t want anything to be executed). ARM isn’t one of them, however.

Thank you.