The infamous “Halt timed out” error occurs when the processor clock is off, so issuing a halt through JTAG has no effect. This may be a serious problem, since you cannot program flash if you cannot halt. If an initialization bug causes the problem, you may not be able to halt the processor quickly enough to get it under control after power-up or reset.
On chips with an ERASE pin, you can escape from this state by erasing flash. You can then reflash your code and set the appropriate GPNVM bit to allow the processor to boot from flash. Unfortunately, some chips in this family lack the external ERASE feature.
A less brutal approach involves hardware reset. It is critical to understand that on these chips, the NRST input is disabled by default. YOUR INITIALIZATION CODE IN FLASH SHOULD TURN ON THE URSTEN BIT IN THE RESET CONTROLLER IMMEDIATELY UPON BOOT (and remember the key, see the chip manual). Do this before fiddling with processor clock setup. Otherwise, to escape from an initialization bug that disables the clock you’ll need the ERASE feature (which your chip may lack).
The OpenOCD command “reset halt” may then work, but it requires some time (~milliseconds) to issue the halt after the reset has been released. That may not be quick enough if the bug is early in the boot code. I find that the sequence “jtag_reset 1 1; halt” followed by “jtag_reset 0 0” reliably halts the CPU before it executes anything. The “halt” command appears to fail, but it puts the chip in a state from which releasing NRST enters the halt state! You must put the last command on a separate line, because otherwise the apparent failure will prevent its execution.
Once you’ve succeeded in halting the chip, you can then reflash as needed.
John Doty
Noqsi Aerospace Ltd