We are starting to test a development environment using the components listed below. The problem that we are facing is that we can’t get the OpenOCD to halt the target. At times that we can we are enabled to inspect the registers, alter the registers, load a binary and execute it. When we try to step the program it works for about 3 steps after that it looses control over the target. For me it seems like a problem related to the JTAG resets, thou I have already tried some combinations parameters of the reset_config [combination] [trst_type] [srst_type].
I have listed the configuration file, the command line used and the log of the openOCD.
At this time we have exausted our knowledge and if someone can help we would appreciate.
environment:
SuSE Linux 10, kernel 2.6.13-15-default
Open On-Chip Debugger (2006-07-15 12:00 CEST)
Amontec JTagkey
libftd2xx0.4.10.tar.gz
Cirrus EDB9302 kit, uses EP9302 (ARM920T) microcontroller
OpenOCD arm9_ftd2xx.cfg:
#daemon configuration
telnet_port 4444
gdb_port 3333
#interface
interface ftd2xx
ftd2xx_device_desc “Amontec JTAGkey A”
ftd2xx_layout “jtagkey”
ftd2xx_vid_pid 0x0403 0xcff8
jtag_speed 1
#use combined on interfaces or targets that can’t set TRST/SRST separately
reset_config trst_and_srst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe
#target configuration
daemon_startup halt
#target
target arm920t little run_and_halt
run_and_halt_time 0 30
Starting the OpenOCD Server
openocd -f doc/configs/arm9_ftd2xx.cfg -d 3 -l openocd.log
OpenOCD telnet command line
Open On-Chip Debugger
reset
halt
requesting target halt…
poll
target state: running
reset halt
reset halt
openocd.log
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: target.c:1275 handle_reset_command():
Debug: arm7_9_common.c:649 arm7_9_assert_reset(): target->state: running
Debug: jtag.c:234 jtag_call_event_callbacks(): jtag event: 0
Debug: jtag.c:1044 jtag_reset_callback():
Debug: ftd2xx.c:614 jtagkey_reset(): trst: 0, srst: 1, high_output: 0x01, high_direction: 0x0f
Debug: arm7_9_common.c:775 arm7_9_halt(): target->state: reset
Debug: embeddedice.c:251 embeddedice_write_reg(): 9: 0xffffffff
Debug: embeddedice.c:251 embeddedice_write_reg(): 11: 0xffffffff
Debug: embeddedice.c:251 embeddedice_write_reg(): 12: 0x00000100
Debug: embeddedice.c:251 embeddedice_write_reg(): 13: 0x000000f7
Debug: arm7_9_common.c:712 arm7_9_deassert_reset(): target->state: reset
Debug: jtag.c:234 jtag_call_event_callbacks(): jtag event: 2
Debug: jtag.c:1044 jtag_reset_callback():
Debug: ftd2xx.c:614 jtagkey_reset(): trst: 0, srst: 0, high_output: 0x09, high_direction: 0x0f
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Another Try
OpenOCD telnet command line
Open On-Chip Debugger
halt
requesting target halt…
target already halted
resume
Target 0 resumed
halt
requesting target halt…
openocd.log
Debug: arm920t.c:291 arm920t_read_cp15_interpreted(): opcode: ee150f30, value: 00000010
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: arm920t.c:291 arm920t_read_cp15_interpreted(): opcode: ee160f10, value: fffff7ff
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: arm920t.c:291 arm920t_read_cp15_interpreted(): opcode: ee160f30, value: 00000000
Debug: target.c:439 target_call_event_callbacks(): target event 0
Info: server.c:67 add_connection(): accepted ‘telnet’ connection from 0
Debug: target.c:1201 handle_halt_command():
Debug: arm7_9_common.c:775 arm7_9_halt(): target->state: halted
Warning: arm7_9_common.c:779 arm7_9_halt(): target was already halted
Debug: target.c:1319 handle_resume_command():
Debug: arm7_9_common.c:1281 arm7_9_resume():
Debug: arm7_9_common.c:1082 arm7_9_restore_context():
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: arm920t.c:381 arm920t_write_cp15_interpreted(): opcode: ee050f10, value: 000000ff, address: 00000000
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: arm920t.c:381 arm920t_write_cp15_interpreted(): opcode: ee050f30, value: 00000010, address: 00000000
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: arm920t.c:381 arm920t_write_cp15_interpreted(): opcode: ee060f10, value: fffff7ff, address: 00000000
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: arm920t.c:381 arm920t_write_cp15_interpreted(): opcode: ee060f30, value: 00000000, address: 00000000
Debug: arm7_9_common.c:1098 arm7_9_restore_context(): examining User mode
Debug: arm7_9_common.c:1112 arm7_9_restore_context(): examining dirty reg: r0
Debug: arm7_9_common.c:1112 arm7_9_restore_context(): examining dirty reg: pc
Debug: arm7_9_common.c:1160 arm7_9_restore_context(): writing register 0 of mode User with value 0x8093009c
Debug: arm7_9_common.c:1098 arm7_9_restore_context(): examining FIQ mode
Debug: arm7_9_common.c:1112 arm7_9_restore_context(): examining dirty reg: pc
Debug: arm7_9_common.c:1098 arm7_9_restore_context(): examining IRQ mode
Debug: arm7_9_common.c:1112 arm7_9_restore_context(): examining dirty reg: pc
Debug: arm7_9_common.c:1098 arm7_9_restore_context(): examining Supervisor mode
Debug: arm7_9_common.c:1112 arm7_9_restore_context(): examining dirty reg: pc
Debug: arm7_9_common.c:1098 arm7_9_restore_context(): examining Abort mode
Debug: arm7_9_common.c:1112 arm7_9_restore_context(): examining dirty reg: pc
Debug: arm7_9_common.c:1098 arm7_9_restore_context(): examining Undefined mode
Debug: arm7_9_common.c:1112 arm7_9_restore_context(): examining dirty reg: pc
Debug: arm7_9_common.c:1199 arm7_9_restore_context(): writing PC with value 0x00000000
Debug: embeddedice.c:251 embeddedice_write_reg(): 0: 0x00000000
Debug: target.c:439 target_call_event_callbacks(): target event 1
Debug: arm7_9_common.c:1384 arm7_9_resume(): target resumed
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: target.c:1201 handle_halt_command():
Debug: arm7_9_common.c:775 arm7_9_halt(): target->state: running
Debug: embeddedice.c:251 embeddedice_write_reg(): 9: 0xffffffff
Debug: embeddedice.c:251 embeddedice_write_reg(): 11: 0xffffffff
Debug: embeddedice.c:251 embeddedice_write_reg(): 12: 0x00000100
Debug: embeddedice.c:251 embeddedice_write_reg(): 13: 0x000000f7
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1
Debug: embeddedice.c:155 embeddedice_read_reg_w_check(): 1