I’m looking for some help with my OpenOCD config file, hopefully someone using the same chip.
I’m making progress, I have the drivers installed, and things are configured up to the point that Eclipse can see the debugger and the debugger seems to be mostly working, but actually running the code seems not to work.
I’m using OpenOCD 0.4.0.
Probably my problems lie in the config file, but I’m not having a lot of luck finding docs that apply to this version of OpenOCD, examples, or the data to roll my own.
Below is what I have so far.
I’m not getting any warnings or errors from OpenOCD.
When I start the debug session, things look ok, but I can’t set a breakpoint (Unresolved breakpoint)
Trying to single-step gives me “Target request failed: putpkt: write failed: No error”
Config file:
Written 4/12/11 DVH
References
http://infocenter.arm.com/help/index.js … GHJJB.html
http://mihirknows.blogspot.com/2007/11/ … -card.html
mS delay from nSRST inactive to JTAG instructions
jtag_nsrst_delay 100
mS delay from nTRST inactive to JTAG instructions
jtag_ntrst_delay 100
#use combined on interfaces or targets that can’t set TRST/SRST separately
reset_config srst_only srst_pulls_trst
Control jtag speed
jtag_khz 2000
set _CHIPNAME at91sam7s
set _ENDIAN little
#5.14.2 ARM7TDMI-S device identification code register
The value we actually get
set _CPUTAPID 0x3f0f0f0f
The value we should get
#set _CPUTAPID 0x7F1F0F0F
#5.14.3 Instruction register length
set _TAPLEN 4
set _IRCAPTURE 1
#5.14.5 Scan chain 1 for comm between the debugger and the ARM7TDMI-S core
Scan chain 2 access to EmbeddedICE-RT registers
To do this, scan chain 2 must be selected using the SCAN_N TAP
controller instruction, and then the TAP controller must be put in INTEST mode.
set cpu 1
#reset_config trst_and_srst|trst_only|srst_only srst_pulls_trst|trst_pulls_srst|combined
reset_config srst_only
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen $_TAPLEN -ircapture $_IRCAPTURE -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
set _CHIP arm7tdmi
set _VARIANT arm7tdmi_r4
set _CHAINPOS 0
#target create $_TARGETNAME $_CHIP -endian $_ENDIAN -chain-position $_CHAINPOS -variant $_VARIANT
target create $_TARGETNAME $_CHIP -endian $_ENDIAN -chain-position $_TARGETNAME -variant $_VARIANT
$_TARGETNAME configure -event reset-init {
disable watchdog
mww 0xfffffd44 0x00008000
enable user reset
mww 0xfffffd08 0xa5000001
CKGR_MOR : enable the main oscillator
mww 0xfffffc20 0x00000601
sleep 10
CKGR_PLLR: 96.1097 MHz
mww 0xfffffc2c 0x00481c0e
sleep 10
PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
mww 0xfffffc30 0x00000007
sleep 10
MC_FMR: flash mode (FWS=1,FMCN=60)
mww 0xffffff60 0x003c0100
sleep 100
wait_halt
flash probe 0
}
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <base_addr> <chip_width> <bus_width> <target_number> [<target_name> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
init
reset init
halt