Hi
I have write cfg files for AT91SAM7A1-EK board from ATEML
here’s a link to the board datasheets
http://www.atmel.com/dyn/resources/prod … oc6114.pdf
and here’s a link to the board processor AT91SAM7A1
http://www.atmel.com/dyn/products/produ … rt_id=3450
I’d like to share the cfg files with the forum members and get feedback if there’s any thing wrong with my cfg files
openocd.cfg
telnet_port 4444
gdb_port 3333
source [find interface/olimex-jtag-tiny.cfg]
#source [find target/at91sam7A1.cfg]
source [find board/atmel_at91sam7A1-ek.cfg]
olimex-jtag-tiny.cfg
#
# Olimex ARM-USB-TINY
#
# http://www.olimex.com/dev/arm-usb-tiny.html
#
interface ft2232
#ft2232_device_desc "Olimex OpenOCD JTAG TINY"
ft2232_device_desc "Olimex OpenOCD JTAG TINY A"
#ft2232_layout olimex-jtag
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15ba 0x0004
atmel_at91sam7A1-ek.cfg
# Atmel AT91SAM7A1-EK
#http://www.atmel.com/dyn/products/tools_card_mcu.asp?tool_id=3490
#www.atmel.com/dyn/resources/prod_documents/doc6114.pdf
set CHIPNAME at91sam7A1
source [find target/at91sam7A1.cfg]
at91sam7A1.cfg
#Atmel AT91SAM7A1
#http://www.atmel.com/dyn/products/product_card.asp?part_id=3450
#SRST & TRST are not connected to JTAG on the board "Hossam"
#jtag_khz 30
reset_config none
set _CHIPNAME at91sam7A1
#force Hardware break points
#gdb_breakpoint_override hard
#TAPID updated to 0x1f0f0f0f after testing.
set _CPUTAPID 0x1f0f0f0f
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME -variant arm7tdmi
#I used boot_iar.s as start up for the board configuration
$_TARGETNAME configure -event reset-init {
# AMC_CSR0 /* set CS0, sandart Wait State, 3 waitstates, 16 bits */
#/* FLASH : Base Address = 0x40000000, CS Enable, Byte Select access, 0 tdf, 4MB, 3 waitstates, 16 bits */
mww 0xFFE00000 0x400030A9
#/* Disable PLL */
#/* PLL/Master clock selection, Key for write access into the CD register (0x1807) */
mww 0xFFFEC004 0x18070004
#/* Set PLL = 13, Divider = 2, Coreclock = 6Mhz * 13 / 2 = 39 Mhz */
#/* Divider 2, PLL = 13, Key for write access into the PDIV register (0x762D)*/
mww 0xFFFEC010 0x762D800D
#/* Enable PLL */
#/* PLL/Master clock selection, Key for write access into the CE register (0x2305)*/
mww 0xFFFEC000 0x23050004
#/* set CS1, sandart Wait State, 0 waitstates, 16 bits */
#/* RAM : Base Address = 0x48000000, CS Enable, Byte Select access, 0 tdf, 4MB, 0 waitstates, 16 bits */
mww 0xFFE00004 0x48003081
#/* set CS2, Disable */
#/* Base Address = 0x50000000 CS Disable */
mww 0xFFE00008 0x50000000
#/* set CS3, Disable */
#/* Base Address = 0x58000000 CS Disable */
mww 0xFFE0000C 0x58000000
#/* set CS6, Disable */
#/* Base Address = 0x70000000 CS Disable */
mww 0xFFE00018 0x70000000
#/* set CS7, Disable */
#/* Base Address = 0x78000000 CS Disable */
mww 0xFFE0001c 0x78000000
#/* 6 Memory Control Register AMC_MCR Value Early Read Protocol, All chip selects valid */
mww 0xFFE00024 0x00000017
#/* Set Remap Bit */
mww 0xFFE00020 0x00000001
}
$_TARGETNAME configure -event reset-assert {
#I don't know what is the meaning of this line but i copy it from IAR mac file
mww 0x000000B4 0x48000000
halt
}
#work Area use internal RAM located at address 0 and with length equals 4K
$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 0
#shutdown OpenOCD daemon when gdb detaches
$_TARGETNAME configure -event gdb-detach { soft_reset_halt; sleep 10; resume; shutdown }
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
set _FLASHNAME $_CHIPNAME.flash
#flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
flash bank $_FLASHNAME cfi 0x40000000 0x2000000 2 2 $_TARGETNAME
# For more information about the configuration files, take a look at:
# openocd.texi
any feedback is welcomed
Salam