I have a small design in Eagle, and the DRC gives errors that don’t make a lot of sense. The following two images show a part of the design and the same part of the DRC image. There are 12mil gaps around conductors, and some of the errors seem to be in plain poured copper. I don’t see anything that’s even questionable. Does anybody know what might be setting off the DRC?
what are the error messages?
One thing that I see is a non-45 deg angle. I turned off DRC “check angle” in the misc tab to get rid of that one. This warns of angles that aren’t a multiple of 45 degrees. This happens when you choose the “straight angled” wire bend tool (3rd from the left) when routing or have a part that is “off grid”. A DSub9 connector is a good example of a part like that but there are lots of others. I will often route from the “off grid” pad rather than to it as that gives slightly better angles.
Error messages from BatchPCB:
EaglePCB-DRC gives a bunch of other errors, but I assume that's because I don't have the correct SparkFun design rules. The whole design is auto-routed by Eagle, so I don't have much control over angles used, etc.Unfortunately your design (xxx) violates our design rules of 8mil
traces with 8mil spacing. Your design has now been deleted.
Top DRC Errors: 72 Bottom DRC Errors: 86
Also, the big yellow “error” area just above the silkscreen for C13 doesn’t have any edges in it – it’s all solid copper. I don’t see how there could be anything wrong around there.
Whoa, rock-n-roll!
After fiddling around for a while, I found some Eagle settings that worked. I ended up increasing the “width” and “isolate” parameters of the groundplane polygons and got through the DRC. I don’t think there were any actual errors, but Eagle probably outputs very thin strips in the Gerber data for a polygon when you use a narrow width. I was using 10 or 12 mil, but I guess that still gives sub-8 mil strips. I’m using 16 mil width and 24 mil isolation now, and that’s good enough for me.
I also autorouted first, then added the polygons. I don’t know whether that makes any difference. I would think that having the polygons in first would permit more efficient routing of signals that are going to ground anyway, but maybe the polygon pouring code also handles that.
Yeah I got some weird errors, I noticed that if I changed my spaceing to like 14 mils, and changed some of my signals to 8mil width I would pass, the DRC bot, but if I go back to my normal 12mil space / 10mil width, the DRC bot fails it but eagle passes it. Strange, but I dont mind changeing some of my signals, even if its just by a few mils, I just have to be careful with that ground plane.
Another thing I noticed, is that the website is telling me my board size is 3.13 by 2.37, but the actual dimension is 3.25 by 2.5 …? there a way to get the DRC bot to include the actual board dimension. Board size is a bit of a limiting factor for me.
Beta testers rule!
Great stuff - thank you thank you.
Ground pours are the number 1 problem. It will reek havoc with the DRC bot. You can route all sorts of stuff, but with a ground pour, there will be many more chances for error.
I am not saying ‘don’t use one’ - in fact, you guys have already found a work around! I’ll be sure and link to the topic. When in doubt, make your ground pours tolerances as large as possible (read : as far away from pads and tracks as possible). I am sorry you have to increase to 14mils. We will try to improve the checking over time to get more accurate DRC passes/fails.
You’ve also discovered the PCB size problems! I taught myself PHP when I took Pittuck’s size script and re-hashed it to work. I scan the top copper layer for max and min sprites in both x and y. What does this mean? I don’t actually catch the edge of the PCB - yet. I hope to re-write the script in the next couple weeks to do a complete scan of all layers.
Either way - don’t worry. Your PCB will be routed to the actual visible edge, not what the bot comes up with. The bot is only ~90% accurate and 90% is sooo much better than what customers could do before, so that’s what we’re going with at the moment.
-Nathan
sparky:
Beta testers rule!…
You’ve also discovered the PCB size problems! I taught myself PHP when I took Pittuck’s size script and re-hashed it to work. I scan the top copper layer for max and min sprites in both x and y. What does this mean? I don’t actually catch the edge of the PCB - yet. I hope to re-write the script in the next couple weeks to do a complete scan of all layers.
Either way - don’t worry. Your PCB will be routed to the actual visible edge, not what the bot comes up with. The bot is only ~90% accurate and 90% is sooo much better than what customers could do before, so that’s what we’re going with at the moment.
-Nathan
I posted on this in another thread. What visible edge are you talking about? None of the 6 gerbers nor the drill file actually have my board edge in them. When the board gets routed, how much is added to avoid copper at the board edge? In eagle, I am using 40 mils. So for my boards, the boarder is usually copper bounding box + 80 mils on each dimension.
To make this really clear, I just submitted a job called “gerb test” with a small area that is actually used. It passed the DRC with a board size of .7 x .55. However the outline is 2.575 x 2.025 and the holes define an area of 2.1x1.7 I know how to make this work (copper pour) so I get close to the right size but as i said in the above paragraph, it’s not clear where the router will actually go.
Even though I am being a-retentive about this, I think you guys have made great progress.
Phil
I posted on this in another thread. What visible edge are you talking about? None of the 6 gerbers nor the drill file actually have my board edge in them. When the board gets routed, how much is added to avoid copper at the board edge? In eagle, I am using 40 mils. So for my boards, the boarder is usually copper bounding box + 80 mils on each dimension.
This is a concern I have too - and here’s how I plan to get around it. I just added the dimension layer to the top silkscreen layer. I figure this should remove any ambiguity about my board size.
It’s easy to do - just select the layer after loading the .cam file, but before you press “Process Job”. I’ve since modified the cam file so this’ll be for every job.
If there’s a better (as in preferred by Nathan) way, lemme know!
Jerry
GeekHollow:
…This is a concern I have too - and here’s how I plan to get around it. I just added the dimension layer to the top silkscreen layer. I figure this should remove any ambiguity about my board size.
It’s easy to do - just select the layer after loading the .cam file, but before you press “Process Job”. I’ve since modified the cam file so this’ll be for every job.
If there’s a better (as in preferred by Nathan) way, lemme know!
Jerry
That won’t work until Nathan scans all gerbers (maybe he could add top silk first…). right now its just the top copper layer. You’d be better off drawing a copper border.
By the way, I use copper pours that are the sixze of the board with isolate at 24 mil and I’ve had no problems. that sort of solves the problem except for the question of where the routing actually happens.
Wow - the forum moves fast these days. Things I fixed on this sunny sunday afternoon:
Board size now checks top copper, bot copper, top over, bottom over, keep out. I think the size will work much better now.
PCB checkout weight fixed. We may have to tweak it a few ounces, but this is pretty arbitrary down the road stuff.
PCB size and cost preview on pages 2 and 3.
Form 2 now autofills for protel file extensions (eagle already supported).
I’m reposting this info on the main sticky as well.
-Nathan
sparky:
Wow - the forum moves fast these days. Things I fixed on this sunny sunday afternoon:Board size now checks top copper, bot copper, top over, bottom over, keep out. I think the size will work much better now.
…
not to mention that you move fast. I think this will work.
Does the PCB house route to the dimensions you come up with or is there some padding?
[edit] I ran a quick couple of tests with the outline in the top silk layer and it seems to be spot on. you guys rock! [/edit]
Philba:
That won’t work until Nathan scans all gerbers (maybe he could add top silk first…). right now its just the top copper layer. You’d be better off drawing a copper border.By the way, I use copper pours that are the sixze of the board with isolate at 24 mil and I’ve had no problems. that sort of solves the problem except for the question of where the routing actually happens.
I do the same pour - but for bottom only. I play with both 16 and 24 mil isolation My logic behind including dimension on top silk screen was for the human element - my understanding is that somebody still has to manually panelize all of these designs together, so adding this in would remove potential guesswork there.
As Nathan has now added all of the layers to the size check, that should now be moot. Or??? I wonder about parts that overhang the board edge (db9, rj45, etc).
Hmm, must try. Be back soon… :twisted:
Jerry
Ok, I’m back 
Just posted my current working design (simple 6-channel 1-Wire interface).
PCB size is 2" x 4", with a RJ-45 jack extending over the long edge. There is a ground plane on the solder size with a width of 16, isolate of 16, that is drawn 25 from the edge. After blowing up the drawing to rediculous size, it appears that this puts the edge of the pour 17 mils from the desired edge of the pcb (that even makes sense - that’s scary).
DRC comes up with 8.4416", price $22.5. When I check the “order me” page, the size is listed as 4" x 2.1104". Obviously the connector is now being included in the estimate (which is what I was expecting to occur). Of course the intended size is 8", which should be a price of $30? 8 x 2.50 = 20, add in $10 and…
So, the question is, what’s the best way to indicate the true pcb size? I have no doubt that it would get figured out during the panneliztion phase, I’m just wondering what could be done to help the automated process. If I knew what was expected out of a keepout layer I bet it could be added to the cam process easily enough…
If Nate or Martyn wants to look at the file - it’s 1WireB.
Jerry
Hey Jerry -
Sounds like the bot is doing exactly what it should 
It’s up to you to trim off anything you don’t want to take up space.
You’re correct, a human has to panelize the designs at this time. This includes anything on the silkscreen layer. We are bad at reading minds so we will panelize whatever you send us.
Caffeine has the evil design for the evening - size of 15940056 sq inches…
-Nathan
Well the size thing works now…does this mean we can buy PCBs now or do we still have to wait.
lol- i was only out for an evening (well got back in the morning)
soo much changed, well done nathan!
[hehe]Nathan dont like my code without comments[/hehe]
I have 6 hours of lab work today, after that i might have a look @ stuff, depends if i am asleep or not…
sparky:
Caffeine has the evil design for the evening - size of 15940056 sq inches…-Nathan
Woohoo! I win! 8)
Great job to Sparkfun, the automated process makes things so easy!
Now if we could just have a cookie set so we don’t have to log in everytime I’d be a very happy man 
Methinks me said that :Dsparky:
Sounds like the bot is doing exactly what it should
This is what concerned me. Eagle makes this damn near impossible to do - you would practically have to design a new part to have the outline terminate at the edge (unless you wanted no part outlines at all - for any part). BUT! After running the silk-gen.ulp all silk screen entities are individual wires - this is now trivial to edit.It’s up to you to trim off anything you don’t want to take up space.
So the process is: Design board. Run silk-gen.ulp. Edit result to clip at the board edge. Export board. Submit, etc.
Now if we just had accurate shipping prices to select from I’d be ready to order… :twisted:
Oh, and as long as I’m wishing, two lines for address would be nice - makes for shipping to the office a bit easier to understand.
111,000 Square Feet? Man, what are you doing? A discrete transister version of a P4? :shock:Caffeine has the evil design for the evening - size of 15940056 sq inches…
Jerry
GeekHollow:
Methinks me said that :Dsparky:
Sounds like the bot is doing exactly what it shouldThis is what concerned me. Eagle makes this damn near impossible to do - you would practically have to design a new part to have the outline terminate at the edge (unless you wanted no part outlines at all - for any part). BUT! After running the silk-gen.ulp all silk screen entities are individual wires - this is now trivial to edit.It’s up to you to trim off anything you don’t want to take up space.
So the process is: Design board. Run silk-gen.ulp. Edit result to clip at the board edge. Export board. Submit, etc.
Jerry
I’m not at all sure why you think eagle makes this near impossible. If you said “eagle libraries are messed up”, I’d agree but there is nothing impossible about it. The library editor is your friend and not that hard to use. Frankly, using library parts without a fair amount of verification is asking for trouble - there are frequent errors.
When it comes to connectors, I usually draw my own after a caliper session with the actual part (even after one with the data sheet). I place the silk screen lines in the tplace layer and all others in the tdoc layer. In particular, the dsub mini parts that extend from the board go in the tdoc layer. Thus, when silk_gen copies the tplace layer to the tsilk layer, all the lines stay inside the board rectangle.
Even if I use the library parts that are tdoc/tplace messed up, I copy the part to a library of my own and change the layers (to tdoc) for the lines that extend from the board. It’s pretty easy to do and takes literally a couple of minutes.
Phil
GeekHollow:
Methinks me said that :Dsparky:
Sounds like the bot is doing exactly what it shouldThis is what concerned me. Eagle makes this damn near impossible to do - you would practically have to design a new part to have the outline terminate at the edge (unless you wanted no part outlines at all - for any part). BUT! After running the silk-gen.ulp all silk screen entities are individual wires - this is now trivial to edit.It’s up to you to trim off anything you don’t want to take up space.
So the process is: Design board. Run silk-gen.ulp. Edit result to clip at the board edge. Export board. Submit, etc.
Now if we just had accurate shipping prices to select from I’d be ready to order… :twisted:
Oh, and as long as I’m wishing, two lines for address would be nice - makes for shipping to the office a bit easier to understand.
111,000 Square Feet? Man, what are you doing? A discrete transister version of a P4? :shock:Caffeine has the evil design for the evening - size of 15940056 sq inches…
Jerry
whats wrong with the shipping prices?