Hi all,
I would like to use Eagle to define electrodes on a small PCB which will be used for an experiment. I happen to need an elliptical electrode, which I had some difficulty in drawing in Eagle. In the end, I chose to implement the ellipse as a large number (~32) of polygon wedges produced by script, as in the following:
http://web.mit.edu/kimt/www/eagleroutin … olygon.PNG
http://web.mit.edu/kimt/www/eagleroutin … lygon2.PNG (after ratsnest)
http://web.mit.edu/kimt/www/eagleroutin … lygon3.PNG
Now, in order to get electrical access to the ‘center’ and ‘ring’ electrodes, I used vias and traces from the corners of the device, as follows:
http://web.mit.edu/kimt/www/eagleroutin … lygon4.PNG
If I now produce the gerber files, I find that the via/backtrace and ring electrodes are considered to be electrically independent, and a finite amount of area around the via is cut away according to the DRC (I believe). So, I went to rename the rear trace to have the same name as the ‘ring’ electrode, but then I find that the ring electrode gets reduced to:
http://web.mit.edu/kimt/www/eagleroutin … lygon5.PNG
http://web.mit.edu/kimt/www/eagleroutin … lygon6.PNG
and I also get a small ‘unrouted line’ between the two vias. The gerber output, according to a viewer, looks identical to the copper (as seen by polygons in real mode) as displayed above in Eagle.
Questions:
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Practical: I want to keep the ring electrode as it is, but have connections through vias. Is there a way that I can enforce this result?
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General: It seems that Eagle is automatically deciding that I don’t need the extra polygons (of the ellipse) on the side, and insisting that I don’t pour copper on it and instead offers this ‘unrouted’ line. What is the logic that Eagle is applying that yields this result?
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More background: It’s also pretty clear that Eagle layout is intended to route signals rather than defining physical electrode shapes (I could not find any other primitives other than straight lines and circular arcs, for instance). For my application, I need specific electrode shapes, and tried to hack a solution through polygon wedges. Will this run into problems down the line in the fabrication? For instance, the CAM process warned me of generating large data in gerber files. I tried reading the gerber output, but didn’t really know how to make sense of it. Is the typical process of PCB manufacture a vector drawing technology, that may get overloaded if I define so many polygons – or does the CAM ‘reduce’ my (bloated) vector data into a simpler form of some kind (i.e. reduce to vector over the actual shape outline, or some sort of raster)?